FR60 MB91460E Series - Microcontrollers - Fujitsu

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MB91460E Series [bit 12] PAUS (A/D converter pause) This bit is set when A/D conversion temporarily halts. The A/D converter has one register to store the conversion result (ADCR) and additionally 32 ADC channel data registers. If a conversion is finished and the data of the previous conversion has not been read out before, previous data would be overwritten. To avoid this problem, the next conversion data is not stored in the data registers until the previous value has been read out (e.g. by DMA). A/D conversion halts during this time. A/D conversion resumes when the ADC interrupt flag ADCR1.INT is cleared. The register protection function depends on the conversion mode and the setting of ADCR2.INTE2: Mode INTE2 Function Single, Stop X Protect ADCR (the common result register) Continous 0 Protect ADCR (the common result register) 1 Protect ADCD0...ADCD31 (the dedicated channel data registers) • In continous mode with INTE2==1, PAUS is set when data of the start channel (set by ADSCH) is ready for writing to the registers, but IRQ2 (End of Scan interrupt) is active. • In the other modes or if INTE2==0, PAUS is set when data of any channel is ready for writing to the registers, but IRQ (End of Conversion) is active. • PAUS is cleared by writing "0" or by a reset. (Not cleared at the end of DMA transfer.) However when waiting condition of DMA transfer, this bit cannot be cleared. • Regarding protect function of converted data, see Section “6. Operation of A/D Converter". [bit 11, 10] STS1, STS0 (Start source select) These bits select the A/D activation source. STS1 STS0 Function 0 0 Software activation [Initial value] 0 1 External trigger pin activation and software activation 1 0 Timer activation and software activation 1 1 External trigger pin activation, timer activation and software activation • These bits are initialized "00" by software reset (RST). • In multiple-activation modes, the first activation to occur starts A/D conversion. • The activation source changes immediately on writing to the register. Therefore care is required when switching activation mode during A/D operation. • The A/D converter detects falling edges on the external trigger pin. When external trigger level is "L" and if these bits are changed to external trigger activation mode, A/D converting may starts. • Selecting the timer selects the 16-bit reload timer 7. 34 DS705-00002-1v3-E
MB91460E Series [bit 9] STRT (Start) Writing "1" to this bit starts A/D conversion (software activation). • Write "1" again to restart conversion. • Initialized to "0" by a software reset (RST). • In continuous and stop mode, restarting is not occurred. Check BUSY bit before writing "1". (Activate conversion after clearing.) • Do not specify forcible termination and software activation (BUSY="0" and STRT="1") at the same time. [bit 8] reserved bit Always write "0" to this bit. • ADCS0 : Access: Half-word, Byte. Read-modify-write access is not allowed 7 6 5 4 3 2 1 0 Bit MD1 MD0 S10 ACH4 ACH3 ACH2 ACH1 ACH0 / ACHMD 0 0 0 0 0 0 0 0 Initial value R/W R/W R/W R R R R R,W * 1 Attribute 1. ACHMD is a new, control bit, see “[bit 0] ACHMD (ACH register mode, write-only)” on page 36. [bit 7, 6] MD1, MD0 (A/D converter mode set) These bits the operation mode. MD1 MD0 Operating mode 0 0 Single mode 1 (Reactivation during A/D conversion is allowed) 0 1 Single mode 2 (Reactivation during A/D conversion is not allowed) 1 0 Continuous mode (Reactivation during A/D conversion is not allowed) 1 1 Stop mode (Reactivation during A/D conversion is not allowed) • Single mode: A/D conversion is continously performed from the selected start channel (ADSCH) to the selected end channel (ADECH). The conversion stops once it has been done for all these channels. • Continuous mode:A/D conversion is repeatedly performed from the selected start channel (ADSCH) to the selected end channel (ADECH) in a row. • Stop mode: A/D conversion is performed from the selected start channel (ADSCH) to the selected end channel (ADECH), followed by a pause after each channel. The conversion is resumed upon activation. When A/D conversion is started in continuous mode or stop mode, conversion operation continued until stopped by the BUSY bit. Conversion is stopped by writing "0" to the BUSY bit. On activation after forcibly stopping, conversion starts from the start channel, selected by ADSCH register. Reactivation during A/D conversion is disabled for any of the timer, external trigger and software start sources in single mode 2, continuous and stop mode. DS705-00002-1v3-E 35
Page 1 and 2: FUJITSU SEMICONDUCTOR DATA SHEET 32
Page 3 and 4: MB91460E Series (Continued) • Rea
Page 5 and 6: MB91460E Series Sound Generator 1 c
Page 7 and 8: MB91460E Series DS705-00002-1v3-E 7
Page 9 and 10: (Continued) Pin no. Pin name I/O 66
Page 15 and 16: 2. Power supply/Ground pins MB91460
Page 17 and 18: Type Circuit Remarks MB91460E Serie
Page 19 and 20: Type Circuit Remarks G Mask ROM and
Page 21 and 22: Type Circuit Remarks M CMOS level t
Page 23 and 24: (Continued) Example of using opposi
Page 25 and 26: ■ NOTES ON DEBUGGER 1. Execution
Page 27 and 28: ■ A/D CONVERTER / RANGE COMPARATO
Page 29 and 30: 3. Block Diagram of A/D Converter T
Page 31 and 32: 1. On MB91F467E, ADC1 does not exis
Page 33: • ADCS1 : Access: Half-word, Byte
Page 37 and 38: 4.2. Common Data Register (ADCR1, A
Page 39 and 40: 4.5. A/D Channel Setting Register (
Page 41 and 42: 5.2. Range Comparator Registers The
Page 43 and 44: 5.2.3. Inverted Range Selection reg
Page 45 and 46: MB91460E Series The interrupt condi
Page 47 and 48: 6. Operation of A/D Converter MB914
Page 49 and 50: 6.5. Scan Conversion The following
Page 51 and 52: MB91460E Series The automatic inter
Page 53 and 54: ■ CLOCK SUPERVISOR (New Feature)
Page 55 and 56: 2.1. Clock Supervisor Control Regis
Page 57 and 58: 3. Block Diagram Clock Supervisor M
Page 59 and 60: MB91460E Series Figure 0-4 Timing D
Page 65 and 66: 4.3. Re-enabling the RC-oscillator
Page 67 and 68: MB91460E Series Figure 0-11 Timing
Page 69 and 70: Timing Diagram: Waking up from Sub
Page 71 and 72: 4.9. RTC mode (STOP mode with Real
Page 73 and 74: 4.11. Check if reset was asserted b
Page 75 and 76: ■ MB91460E Series DS705-00002-1v3
Page 77 and 78: 2. Standby RAM MB91460E Series MB91
Page 79 and 80: 3.3. EXTE: Shutdown recovery extern
Page 81 and 82: [bit 1] RTCF: Real Time Clock recov
Page 83 and 84: 3.6. EXTLV1/2: Shutdown recovery ex
Page 85 and 86:
4.1.3. Shutdown with Real Time Cloc
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4.1.8. External Interrupts: Level o
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4.3. Determining the Reset Source a
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4.5. I/O Behaviour in Shutdown Duri
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3. Programming model 3.1. Basic pro
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4.3. CCR (Condition Code Register)
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■ EMBEDDED PROGRAM/DATA MEMORY (F
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3.2. Flash access timing settings i
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4. Parallel Flash programming mode
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5. Poweron Sequence in parallel pro
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6.3. Security Vector FSV2 MB91460E
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■ MEMORY MAPS 1. MB91F467EA 00000
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Address 000000H 000004H 000008H Reg
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(Continued) Address 0000A0H Registe
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(Continued) Address 000180H Reserve
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(Continued) Address 000200H 000204H
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(Continued) Address 000348H 00034CH
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(Continued) Address 00048CH 000490H
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(Continued) Address + 0 + 1 Registe
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Address 000704H 000708H 00070CH 000
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(Continued) Address 000D80H 000D84H
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(Continued) Address 000E80H 000E84H
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(Continued) Address 002000H to 006F
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(Continued) Address 00C080H 00C084H
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(Continued) Address 00C1A0H 00C1A4H
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Address 00F09CH 00F0A0H 00F0A4H 00F
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32bit read/write dat[31:0] dat[31:0
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(Continued) Interrupt Decimal Inter
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(Continued) Interrupt Decimal Inter
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■ RECOMMENDED SETTINGS 1. PLL and
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MB91460E Series (Continued) Modulat
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MB91460E Series (Continued) Modulat
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(Continued) Modulation Degree (k) R
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“H” level average output curren
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2. Recommended operating conditions
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3. DC characteristics MB91460E Seri
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Parameter Symbol Analog inputleakag
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MB91460E Series 4. A/D converter ch
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Digital output 3FFH 3FEH 3FDH 004H
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5. Alarm comparator characteristics
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7. AC characteristics 7.1. Clock ti
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7.3. LIN-USART Timings at VDD5 = 3.
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7.4. I 2 C AC Timings at VDD5 = 3.0
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7.5. Free-run timer clock Input pul
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.7.4. Synchronous
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MB91460E Series 7.7.6. Asynchronous
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7.7.8. RDY waitcycle insertion Para
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7.7.10. Clock relationships MB91460
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MCLKO DACKX DEOP delayed DACKX dela
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.8.4. Synchronous
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MB91460E Series 7.8.6. Asynchronous
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7.8.8. RDY waitcycle insertion Para
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7.8.10. Clock relationships MCLKO
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MCLKO DACKX DEOP delayed DACKX dela
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■ PACKAGE DIMENSION 208-pin plast
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Version/ Date Ver. 0.8 2009-10-19 V
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■ CHANGES IN THIS EDITION DS705-0
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MEMO MB91460E Series DS705-00002-1v
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MB91460E Series DS705-00002-1v3-E 2
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FR60 MB91460E Series - Microcontrollers - Fujitsu

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