FR60 MB91460E Series - Microcontrollers - Fujitsu

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MB91460E Series Table 0-1 describes the function of each bit of the Clock Supervisor Control Register (CSVCR). Table 0-1 Functional Description of each bit of the Clock Supervisor Control Register Bit Name Function 7 6 5 4 3 2 1 0 SCKS (Sub clock select) MM (Main clock missing) SM (Sub clock missing) RCE (RC-oscillator enable) MSVE (Main clock supervisor enable) SSVE (Sub clock supervisorenable) SRST (Sub clock mode reset) OUTE (Output enable) This bit is to select between 32 kHz external oscillation and internal RC oscillation as Sub clock. If this bit is ‘0’ then the external 32 kHz oscillation is used as Sub clock, if it’s ‘1’ then the internal RC oscillation is used as Sub clock. This bit is cleared to ’0’ by Power-On reset or external reset. Other types of reset will not affect this bit. Note: Don’t change this bit while the CPU runs on Sub clock. First switch back to Main clock and then change SCKS! If this bit is 1, the Main clock supervisor has detected that the Main oscillation clock coming from X0, X1 is missing, e.g. by a broken crystal. If this bit is ‘0’, a missing Main clock has not been detected. This bit is cleared to ’0’ by Power-On reset or external reset. Other types of reset will not affect this bit. New feature: This bit can be cleared by CPU access, if the main oscillator has resumed oscillation. If the main oscillator is still failing, the write access is ignored. If this bit is 1, the Sub clock supervisor has detected that the sub oscillation clock coming from X0A, X1A is missing, e.g. by a broken crystal. If this bit is ‘0’, a missing Sub clock has not been detected. This bit is cleared to ’0’ by Power-On reset or external reset. Other types of reset will not affect this bit. New feature: This bit can be cleared by CPU access, if the sub oscillator has resumed oscillation. If the sub oscillator is still failing, the write access is ignored. Setting this bit to ‘1’ enables the RC-oscillator in STOP mode. Outside STOP mode, the RC-oscillator is always enabled. This bit is set to ’1’ by Power-On reset or external reset. Other types of reset will not affect this bit. New feature: If HWWDE.STP_RUN (=HWWDE[4]) is set in the Hardware Watchdog, then the RC oscillator is enabled and read and read-modify-write operations will return ‘1’ independendly of RCE register setting. Effective RCE = RCE_Register or HWWDE.STP_RUN Setting this bit to ‘1’ enables the Main clock supervisor. This bit is set to ’1’ by Power-On reset only. Other types of reset will not affect this bit. Setting this bit to ‘1’ enables the Sub clock supervisor. This bit is set to ’1’ by Power-On reset only. Other types of reset will not affect this bit. If this bit is set to ‘1’, a reset is performed upon transition from Main/PLL clock mode to Sub clock mode if the Sub clock is already missing. If this bit is set to ‘0’, no reset is performed in this case. This bit is cleared to ’0’ by Power-On reset or external reset. Other types of reset will not affect this bit. This bit can be used as an output enable to output the signals MCLK_MISSING (bit 3 of CSVCR) and SCLK_MISSING (bit 4 of CSVCR) to port pins. For more information about the pins see the corresponding Datasheet. If this bit is set to ’1’, the ports are enabled for MCLK_MISSING and SCLK_MISSING output. This bit is cleared to ’0’ by Power-On reset or external reset. Other types of reset will not affect this bit. 56 DS705-00002-1v3-E
3. Block Diagram Clock Supervisor MB91460E Series This section presents a block diagram of the Clock Supervisor. The building blocks of the Clock Supervisor are: • Main Clock Supervisor • Sub Clock Supervisor • Control Logic • RC-Oscillator 3.1. Block Diagram Clock Supervisor EXT_RST_IN PONR OSC_STAB OSCMAIN MCLK_STBY OSCSUB SCLK_STBY RC_CLK Figure 0-3 Bock Diagram of Clock Supervisor ERSX PONR TB_ST SCLK_STBY SSEN MCLK_STBY MSEN RC_CLK RC_CLK R-Bus Clock Supervisor Control Logic Clock Supervisor Control Register CSVCR 7 6 5 4 3 2 1 0 SCKS MM SM RCE MSVE SSVE SRST OUTE Timeout Counter CLK TO_MCLK TO_SCLK Main Clock Supervisor MCLK NO_MCLK EN STBY RC_CLK Sub Clock Supervisor SCLK NO_SCLK EN STBY RC_CLK SCLK_OUT and MCLK_OUT can be observed using the Clock Monitor Module. SCLK_MISSING and MCLK_MISSING can be programmed to device specific outputs (see the datasheet of the used device for the information which pins are used) by setting OUTE=1. DS705-00002-1v3-E 57 ERSXO SM SCKS MM NO_MCLK RCE NO_SCLK RC_CLK f/2 RC_CLK 0 1 0 1 RC-Oscillator STBY RC_CLK RC_CLK S MUX S MUX OR EXT_RST_OUT OUTE SCLK_MISSING MCLK_MISSING CLKMAIN CLKSUB
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FUJITSU SEMICONDUCTOR DATA SHEET 32
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MB91460E Series (Continued) • Rea
Page 5 and 6: MB91460E Series Sound Generator 1 c
Page 7 and 8: MB91460E Series DS705-00002-1v3-E 7
Page 9 and 10: (Continued) Pin no. Pin name I/O 66
Page 15 and 16: 2. Power supply/Ground pins MB91460
Page 17 and 18: Type Circuit Remarks MB91460E Serie
Page 19 and 20: Type Circuit Remarks G Mask ROM and
Page 21 and 22: Type Circuit Remarks M CMOS level t
Page 23 and 24: (Continued) Example of using opposi
Page 25 and 26: ■ NOTES ON DEBUGGER 1. Execution
Page 27 and 28: ■ A/D CONVERTER / RANGE COMPARATO
Page 29 and 30: 3. Block Diagram of A/D Converter T
Page 31 and 32: 1. On MB91F467E, ADC1 does not exis
Page 33 and 34: • ADCS1 : Access: Half-word, Byte
Page 35 and 36: MB91460E Series [bit 9] STRT (Start
Page 37 and 38: 4.2. Common Data Register (ADCR1, A
Page 39 and 40: 4.5. A/D Channel Setting Register (
Page 41 and 42: 5.2. Range Comparator Registers The
Page 43 and 44: 5.2.3. Inverted Range Selection reg
Page 45 and 46: MB91460E Series The interrupt condi
Page 47 and 48: 6. Operation of A/D Converter MB914
Page 49 and 50: 6.5. Scan Conversion The following
Page 51 and 52: MB91460E Series The automatic inter
Page 53 and 54: ■ CLOCK SUPERVISOR (New Feature)
Page 55: 2.1. Clock Supervisor Control Regis
Page 59 and 60: MB91460E Series Figure 0-4 Timing D
Page 65 and 66: 4.3. Re-enabling the RC-oscillator
Page 67 and 68: MB91460E Series Figure 0-11 Timing
Page 69 and 70: Timing Diagram: Waking up from Sub
Page 71 and 72: 4.9. RTC mode (STOP mode with Real
Page 73 and 74: 4.11. Check if reset was asserted b
Page 75 and 76: ■ MB91460E Series DS705-00002-1v3
Page 77 and 78: 2. Standby RAM MB91460E Series MB91
Page 79 and 80: 3.3. EXTE: Shutdown recovery extern
Page 81 and 82: [bit 1] RTCF: Real Time Clock recov
Page 83 and 84: 3.6. EXTLV1/2: Shutdown recovery ex
Page 85 and 86: 4.1.3. Shutdown with Real Time Cloc
Page 87 and 88: 4.1.8. External Interrupts: Level o
Page 89 and 90: 4.3. Determining the Reset Source a
Page 91 and 92: 4.5. I/O Behaviour in Shutdown Duri
Page 93 and 94: 3. Programming model 3.1. Basic pro
Page 95 and 96: 4.3. CCR (Condition Code Register)
Page 97 and 98: ■ EMBEDDED PROGRAM/DATA MEMORY (F
Page 99 and 100: 3.2. Flash access timing settings i
Page 101 and 102: 4. Parallel Flash programming mode
Page 103 and 104: 5. Poweron Sequence in parallel pro
Page 105 and 106: 6.3. Security Vector FSV2 MB91460E
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■ MEMORY MAPS 1. MB91F467EA 00000
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Address 000000H 000004H 000008H Reg
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(Continued) Address 0000A0H Registe
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(Continued) Address 000180H Reserve
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(Continued) Address 000200H 000204H
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(Continued) Address 000348H 00034CH
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(Continued) Address 00048CH 000490H
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(Continued) Address + 0 + 1 Registe
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Address 000704H 000708H 00070CH 000
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(Continued) Address 000D80H 000D84H
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(Continued) Address 000E80H 000E84H
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(Continued) Address 002000H to 006F
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(Continued) Address 00C080H 00C084H
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(Continued) Address 00C1A0H 00C1A4H
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Address 00F09CH 00F0A0H 00F0A4H 00F
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32bit read/write dat[31:0] dat[31:0
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(Continued) Interrupt Decimal Inter
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(Continued) Interrupt Decimal Inter
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■ RECOMMENDED SETTINGS 1. PLL and
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MB91460E Series (Continued) Modulat
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MB91460E Series (Continued) Modulat
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(Continued) Modulation Degree (k) R
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“H” level average output curren
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2. Recommended operating conditions
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3. DC characteristics MB91460E Seri
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Parameter Symbol Analog inputleakag
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MB91460E Series 4. A/D converter ch
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Digital output 3FFH 3FEH 3FDH 004H
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5. Alarm comparator characteristics
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7. AC characteristics 7.1. Clock ti
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7.3. LIN-USART Timings at VDD5 = 3.
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7.4. I 2 C AC Timings at VDD5 = 3.0
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7.5. Free-run timer clock Input pul
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.7.4. Synchronous
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MB91460E Series 7.7.6. Asynchronous
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7.7.8. RDY waitcycle insertion Para
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7.7.10. Clock relationships MB91460
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MCLKO DACKX DEOP delayed DACKX dela
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.8.4. Synchronous
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MB91460E Series 7.8.6. Asynchronous
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7.8.8. RDY waitcycle insertion Para
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7.8.10. Clock relationships MCLKO
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MCLKO DACKX DEOP delayed DACKX dela
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■ PACKAGE DIMENSION 208-pin plast
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Version/ Date Ver. 0.8 2009-10-19 V
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■ CHANGES IN THIS EDITION DS705-0
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MEMO MB91460E Series DS705-00002-1v
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MB91460E Series DS705-00002-1v3-E 2
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FR60 MB91460E Series - Microcontrollers - Fujitsu

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