FR60 MB91460E Series - Microcontrollers - Fujitsu

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MB91460E Series 7.8.9. Bus hold timing (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0V,TA =−40 °C to + 105 °C) Parameter Symbol Pin name Value Min Max MCLKO ↓ to BGRNTX delay time tCLBGL tCLBGH MCLKO BGRNTX ⎯ ⎯ 5 6 ns ns Bus HIZ to BGRNTX ↓ tAXBGL BGRNTX MCLK* A0 to An tCLKT + 8 ⎯ ns BGRNTX ↑ to Bus drive tBGHAV RDX, ASX WRXn,WEX CSXn,BAAX tCLKT + 1 ⎯ ns Note : BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX). It must be kept High as long as the bus shall be hold. After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX. Note : Condition for tAXBGL and tBGHAV : - VOL = 0.2 × VDD35 - VOH = 0.8 × VDD35 MCLKO BRQ BGRNTX ADDR, RDX, WRX, WEX, CSXn, ASX, MCLKE, MCLKI, MCLKO, BAAX tCLBGL tCLBGH tAXBGL tBGHAV 196 DS705-00002-1v3-E Unit
7.8.10. Clock relationships MCLKO ↓ to MCLKE (in sleep mode) Parameter Symbol Pin name MCLKO MCLKE(sleep) MB91460E Series (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0V,TA =−40 °C to + 105 °C) Value Min Max DS705-00002-1v3-E 197 Unit tCLML MCLKO ⎯ 3 ns tCLMH MCLKE 0 ⎯ ns tCLML tCLMH
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FUJITSU SEMICONDUCTOR DATA SHEET 32
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MB91460E Series (Continued) • Rea
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MB91460E Series Sound Generator 1 c
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MB91460E Series DS705-00002-1v3-E 7
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(Continued) Pin no. Pin name I/O 66
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2. Power supply/Ground pins MB91460
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Type Circuit Remarks MB91460E Serie
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Type Circuit Remarks G Mask ROM and
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Type Circuit Remarks M CMOS level t
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(Continued) Example of using opposi
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■ NOTES ON DEBUGGER 1. Execution
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■ A/D CONVERTER / RANGE COMPARATO
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3. Block Diagram of A/D Converter T
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1. On MB91F467E, ADC1 does not exis
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• ADCS1 : Access: Half-word, Byte
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MB91460E Series [bit 9] STRT (Start
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4.2. Common Data Register (ADCR1, A
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4.5. A/D Channel Setting Register (
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5.2. Range Comparator Registers The
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5.2.3. Inverted Range Selection reg
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MB91460E Series The interrupt condi
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6. Operation of A/D Converter MB914
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6.5. Scan Conversion The following
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MB91460E Series The automatic inter
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■ CLOCK SUPERVISOR (New Feature)
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2.1. Clock Supervisor Control Regis
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3. Block Diagram Clock Supervisor M
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MB91460E Series Figure 0-4 Timing D
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4.3. Re-enabling the RC-oscillator
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MB91460E Series Figure 0-11 Timing
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Timing Diagram: Waking up from Sub
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4.9. RTC mode (STOP mode with Real
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4.11. Check if reset was asserted b
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■ MB91460E Series DS705-00002-1v3
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2. Standby RAM MB91460E Series MB91
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3.3. EXTE: Shutdown recovery extern
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[bit 1] RTCF: Real Time Clock recov
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3.6. EXTLV1/2: Shutdown recovery ex
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4.1.3. Shutdown with Real Time Cloc
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4.1.8. External Interrupts: Level o
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4.3. Determining the Reset Source a
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4.5. I/O Behaviour in Shutdown Duri
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3. Programming model 3.1. Basic pro
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4.3. CCR (Condition Code Register)
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■ EMBEDDED PROGRAM/DATA MEMORY (F
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3.2. Flash access timing settings i
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4. Parallel Flash programming mode
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5. Poweron Sequence in parallel pro
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6.3. Security Vector FSV2 MB91460E
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■ MEMORY MAPS 1. MB91F467EA 00000
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Address 000000H 000004H 000008H Reg
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(Continued) Address 0000A0H Registe
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(Continued) Address 000180H Reserve
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(Continued) Address 000200H 000204H
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(Continued) Address 000348H 00034CH
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(Continued) Address 00048CH 000490H
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(Continued) Address + 0 + 1 Registe
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Address 000704H 000708H 00070CH 000
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(Continued) Address 000D80H 000D84H
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(Continued) Address 000E80H 000E84H
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(Continued) Address 002000H to 006F
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(Continued) Address 00C080H 00C084H
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(Continued) Address 00C1A0H 00C1A4H
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Address 00F09CH 00F0A0H 00F0A4H 00F
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32bit read/write dat[31:0] dat[31:0
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(Continued) Interrupt Decimal Inter
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(Continued) Interrupt Decimal Inter
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■ RECOMMENDED SETTINGS 1. PLL and
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Page 149 and 150: (Continued) Modulation Degree (k) R
Page 151 and 152: “H” level average output curren
Page 153 and 154: 2. Recommended operating conditions
Page 155 and 156: 3. DC characteristics MB91460E Seri
Page 157 and 158: Parameter Symbol Analog inputleakag
Page 159 and 160: MB91460E Series 4. A/D converter ch
Page 161 and 162: Digital output 3FFH 3FEH 3FDH 004H
Page 163 and 164: 5. Alarm comparator characteristics
Page 165 and 166: 7. AC characteristics 7.1. Clock ti
Page 167 and 168: 7.3. LIN-USART Timings at VDD5 = 3.
Page 169 and 170: 7.4. I 2 C AC Timings at VDD5 = 3.0
Page 171 and 172: 7.5. Free-run timer clock Input pul
Page 173 and 174: MCLKO CSXn delayed CSXn ASX ADDRESS
Page 175 and 176: MCLKO MCLKI CSXn WRXn (as byte enab
Page 177 and 178: MB91460E Series 7.7.4. Synchronous
Page 179 and 180: MB91460E Series 7.7.6. Asynchronous
Page 181 and 182: 7.7.8. RDY waitcycle insertion Para
Page 183 and 184: 7.7.10. Clock relationships MB91460
Page 185 and 186: MCLKO DACKX DEOP delayed DACKX dela
Page 187 and 188: MCLKO CSXn delayed CSXn ASX ADDRESS
Page 189 and 190: MCLKO MCLKI CSXn WRXn (as byte enab
Page 191 and 192: MB91460E Series 7.8.4. Synchronous
Page 193 and 194: MB91460E Series 7.8.6. Asynchronous
Page 195: 7.8.8. RDY waitcycle insertion Para
Page 199 and 200: MCLKO DACKX DEOP delayed DACKX dela
Page 201 and 202: ■ PACKAGE DIMENSION 208-pin plast
Page 203 and 204: Version/ Date Ver. 0.8 2009-10-19 V
Page 205 and 206: ■ CHANGES IN THIS EDITION DS705-0
Page 207 and 208: MEMO MB91460E Series DS705-00002-1v
Page 209: MB91460E Series DS705-00002-1v3-E 2
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FR60 MB91460E Series - Microcontrollers - Fujitsu

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