FR60 MB91460E Series - Microcontrollers - Fujitsu

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MB91460E Series If the timeout is reached, the Hardware Watchdog generates INIT, which cancelles the Shutdown state and forces recovery. The CPU will run on Main Oscillation after this recovery. WARNING: If a Hardware Watchdog timeout INIT signal appeares just at the transition to Standby Mode, the device may enter an unpredictable state. Always make sure that the hardware Watchdog has been cleared just before entering Shutdown. 4.1.5. Clock Supervisor in Shutdown The INITX pin, Clock Supervisor and Hardware Watchdog form the “external INIT chain”, like shown in the figure in section “Determining the Reset Source after Shutdown” on page 89. The Shutdown control is part of this chain. An INIT signal from the Clock Supervisor will pass the Hardware Watchdog and arrive at the same Shutdown control input line as the INIT signal from Hardware Watchdog. Therefore, clock supervision in Shutdown mode is only possible if the Hardware Watchdog is operating in parallel. If the Hardware Watchdog is disabled in Shutdown mode, an INIT signal from the Clock Supervisor is ignored in Shutdown. The Clock Supervisor is enabled by default. In Shutdown mode, as long as the Main- and/or Sub-oscillator is running and the RC clock is not stopped, the CSV is supervising the Main- or Sub-oscillator, respectively. • The Clock Supervisor needs the RC clock, so set CSVCR.RCE=1, this is default setting. • If the Main-oscillator is not stopped (STCR.OSCD1=0), the Main clock supervisor is running. • If the Main-oscillator fails, the Main Clock Supervisor generates INIT, which can cancel the Shutdown state and force recovery. The CPU runs on RC clock during and after the recovery. • If the Sub-oscillator is not stopped (STCR.OSCD2=0), the Sub Clock Supervisor is running. • If the Sub-oscillator fails, the Sub clock is switched to RC clock divided by 2. An INIT is not generated, and the Real Time Clock continues running on on RC clock divided by 2, if RTC is enabled. To disable the Clock Supervisor, clear the bits CSVCR.MSVE and CSVCR.SSVE. 4.1.6. Low Voltage Detection in Shutdown Low Voltage Detection is not supported in Shutdown mode. Always set the Low Voltage Detection into power down mode (LVDET.LVEPD=1, LVDET.LVIPD=1) before enabling Shutdown. 4.1.7. External Interrupts: Input Voltage Setting The input voltages (CMOS-Schmitt, Automotive, TTL, CMOS-2) of the external interrupt lines are defined by the setting of PILR and EPILR of the appropriate ports. The PILR and EPILR settings for the 8 external recovery interrupt lines are maintained during Shutdown mode until they are cleared by the Software reset following the Recovery INIT. EPILR PILR Pin No Pin Name EPILR23[2] PILR23[2] 93 P23_2/RX1/INT9 EPILR23[0] PILR23[0] 91 P23_0/RX0/INT8 EPILR24[7] PILR24[7] 90 P24_7/SCL3/INT7C EPILR24[6] PILR24[6] 89 P24_6/SDA3/INT6D EPILR24[3] PILR24[3] 86 P24_3/INT3 EPILR24[2] PILR24[2] 85 P24_2/INT2 EPILR24[1] PILR24[1] 84 P24_1/INT1 EPILR24[0] PILR24[0] 83 P24_0/INT0 86 DS705-00002-1v3-E
4.1.8. External Interrupts: Level or Edge Setting MB91460E Series The registers EXTLV1 and EXTLV2 are used to set the interrupt level or edge for recovery per interrupt channel. LBx LAx Interrupt Level 0 0 "L" level (initial value) 0 1 "H" level 1 0 Rising edge 1 1 Falling edge The settings “level” and “edge” generate different behaviour if the external source line is not changed back after recovery of if it changes to the sensitive level before Shutdown. Examples: • INT0 is enabled for recovery on risong edge. If a rising edge appeares during Shutdown state, recovery is performed. If a rising edge is outside Shutdown state, there will be no recovery: INT0 STOP/ShutDown state Recovery INIT • INT0 is enabled for recovery on high level. If INT0 changes to high level during Shutdown state, recovery is performed. If INT0 changes to high level already before Shutdown state, the Shutdown is recovered immediately because the high level on INT0 is valid. Note that, in this case, a complete shut-down/power-up sequence with recovery INIT is performed: INT0 STOP/ShutDown state Recovery INIT Note: If “H” level or “L” level is enabled for recovery, the level must be active for minimum 500 µs. DS705-00002-1v3-E 87
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FUJITSU SEMICONDUCTOR DATA SHEET 32
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MB91460E Series (Continued) • Rea
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MB91460E Series Sound Generator 1 c
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MB91460E Series DS705-00002-1v3-E 7
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(Continued) Pin no. Pin name I/O 66
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2. Power supply/Ground pins MB91460
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Type Circuit Remarks MB91460E Serie
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Type Circuit Remarks G Mask ROM and
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Type Circuit Remarks M CMOS level t
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(Continued) Example of using opposi
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■ NOTES ON DEBUGGER 1. Execution
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■ A/D CONVERTER / RANGE COMPARATO
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3. Block Diagram of A/D Converter T
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1. On MB91F467E, ADC1 does not exis
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• ADCS1 : Access: Half-word, Byte
Page 35 and 36: MB91460E Series [bit 9] STRT (Start
Page 37 and 38: 4.2. Common Data Register (ADCR1, A
Page 39 and 40: 4.5. A/D Channel Setting Register (
Page 41 and 42: 5.2. Range Comparator Registers The
Page 43 and 44: 5.2.3. Inverted Range Selection reg
Page 45 and 46: MB91460E Series The interrupt condi
Page 47 and 48: 6. Operation of A/D Converter MB914
Page 49 and 50: 6.5. Scan Conversion The following
Page 51 and 52: MB91460E Series The automatic inter
Page 53 and 54: ■ CLOCK SUPERVISOR (New Feature)
Page 55 and 56: 2.1. Clock Supervisor Control Regis
Page 57 and 58: 3. Block Diagram Clock Supervisor M
Page 59 and 60: MB91460E Series Figure 0-4 Timing D
Page 65 and 66: 4.3. Re-enabling the RC-oscillator
Page 67 and 68: MB91460E Series Figure 0-11 Timing
Page 69 and 70: Timing Diagram: Waking up from Sub
Page 71 and 72: 4.9. RTC mode (STOP mode with Real
Page 73 and 74: 4.11. Check if reset was asserted b
Page 75 and 76: ■ MB91460E Series DS705-00002-1v3
Page 77 and 78: 2. Standby RAM MB91460E Series MB91
Page 79 and 80: 3.3. EXTE: Shutdown recovery extern
Page 81 and 82: [bit 1] RTCF: Real Time Clock recov
Page 83 and 84: 3.6. EXTLV1/2: Shutdown recovery ex
Page 85: 4.1.3. Shutdown with Real Time Cloc
Page 89 and 90: 4.3. Determining the Reset Source a
Page 91 and 92: 4.5. I/O Behaviour in Shutdown Duri
Page 93 and 94: 3. Programming model 3.1. Basic pro
Page 95 and 96: 4.3. CCR (Condition Code Register)
Page 97 and 98: ■ EMBEDDED PROGRAM/DATA MEMORY (F
Page 99 and 100: 3.2. Flash access timing settings i
Page 101 and 102: 4. Parallel Flash programming mode
Page 103 and 104: 5. Poweron Sequence in parallel pro
Page 105 and 106: 6.3. Security Vector FSV2 MB91460E
Page 107 and 108: ■ MEMORY MAPS 1. MB91F467EA 00000
Page 109 and 110: Address 000000H 000004H 000008H Reg
Page 111 and 112: (Continued) Address 0000A0H Registe
Page 113 and 114: (Continued) Address 000180H Reserve
Page 115 and 116: (Continued) Address 000200H 000204H
Page 117 and 118: (Continued) Address 000348H 00034CH
Page 119 and 120: (Continued) Address 00048CH 000490H
Page 121 and 122: (Continued) Address + 0 + 1 Registe
Page 123 and 124: Address 000704H 000708H 00070CH 000
Page 125 and 126: (Continued) Address 000D80H 000D84H
Page 127 and 128: (Continued) Address 000E80H 000E84H
Page 129 and 130: (Continued) Address 002000H to 006F
Page 131 and 132: (Continued) Address 00C080H 00C084H
Page 133 and 134: (Continued) Address 00C1A0H 00C1A4H
Page 135 and 136: Address 00F09CH 00F0A0H 00F0A4H 00F
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32bit read/write dat[31:0] dat[31:0
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(Continued) Interrupt Decimal Inter
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(Continued) Interrupt Decimal Inter
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■ RECOMMENDED SETTINGS 1. PLL and
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MB91460E Series (Continued) Modulat
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MB91460E Series (Continued) Modulat
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(Continued) Modulation Degree (k) R
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“H” level average output curren
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2. Recommended operating conditions
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3. DC characteristics MB91460E Seri
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Parameter Symbol Analog inputleakag
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MB91460E Series 4. A/D converter ch
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Digital output 3FFH 3FEH 3FDH 004H
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5. Alarm comparator characteristics
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7. AC characteristics 7.1. Clock ti
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7.3. LIN-USART Timings at VDD5 = 3.
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7.4. I 2 C AC Timings at VDD5 = 3.0
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7.5. Free-run timer clock Input pul
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.7.4. Synchronous
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MB91460E Series 7.7.6. Asynchronous
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7.7.8. RDY waitcycle insertion Para
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7.7.10. Clock relationships MB91460
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MCLKO DACKX DEOP delayed DACKX dela
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.8.4. Synchronous
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MB91460E Series 7.8.6. Asynchronous
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7.8.8. RDY waitcycle insertion Para
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7.8.10. Clock relationships MCLKO
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MCLKO DACKX DEOP delayed DACKX dela
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■ PACKAGE DIMENSION 208-pin plast
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Version/ Date Ver. 0.8 2009-10-19 V
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■ CHANGES IN THIS EDITION DS705-0
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MEMO MB91460E Series DS705-00002-1v
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MB91460E Series DS705-00002-1v3-E 2
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FR60 MB91460E Series - Microcontrollers - Fujitsu

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