FR60 MB91460E Series - Microcontrollers - Fujitsu

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MB91460E Series ■ HANDLING DEVICES 1. Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage higher than (VDD5, VDD35 or HVDD5) or less than (VSS5 orHVSS5) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings. 2. Handling of unused input pins If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistor (2KΩ to 10KΩ) or enable internal pullup or pulldown resisters (PPER/PPCR) before the input enable (PORTEN) is activated by software. The mode pins MD_x can be connected to VSS5 or VDD5 directly. Unused ALARM input pins can be connected to AVSS5 directly. 3. Power supply pins In MB91460 series, devices including multiple power supply pins and ground pins are designed as follows; pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latch-up. All of the power supply pins and ground pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of the MB91460 series must be connected to the current supply source via a low impedance. It is also recommended to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between power supply pin and ground pin near this device. This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 µF (use a X7R ceramic capacitator) to VCC18C pin for the regulator. 4. Crystal oscillator circuit Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground. It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and X1A pins are surrounded by ground plane for the stable operation. Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this device. 5. Notes on using external clock When using the external clock, it is necessary to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In the described combination, X1 (X1A) should be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. At X0 and X1, a frequency up to 16 MHz is possible. (Continued) 22 DS705-00002-1v3-E
(Continued) Example of using opposite phase supply X0 (X0A) X1 (X1A) MB91460E Series DS705-00002-1v3-E 23
Page 1 and 2: FUJITSU SEMICONDUCTOR DATA SHEET 32
Page 3 and 4: MB91460E Series (Continued) • Rea
Page 5 and 6: MB91460E Series Sound Generator 1 c
Page 7 and 8: MB91460E Series DS705-00002-1v3-E 7
Page 9 and 10: (Continued) Pin no. Pin name I/O 66
Page 15 and 16: 2. Power supply/Ground pins MB91460
Page 17 and 18: Type Circuit Remarks MB91460E Serie
Page 19 and 20: Type Circuit Remarks G Mask ROM and
Page 21: Type Circuit Remarks M CMOS level t
Page 25 and 26: ■ NOTES ON DEBUGGER 1. Execution
Page 27 and 28: ■ A/D CONVERTER / RANGE COMPARATO
Page 29 and 30: 3. Block Diagram of A/D Converter T
Page 31 and 32: 1. On MB91F467E, ADC1 does not exis
Page 33 and 34: • ADCS1 : Access: Half-word, Byte
Page 35 and 36: MB91460E Series [bit 9] STRT (Start
Page 37 and 38: 4.2. Common Data Register (ADCR1, A
Page 39 and 40: 4.5. A/D Channel Setting Register (
Page 41 and 42: 5.2. Range Comparator Registers The
Page 43 and 44: 5.2.3. Inverted Range Selection reg
Page 45 and 46: MB91460E Series The interrupt condi
Page 47 and 48: 6. Operation of A/D Converter MB914
Page 49 and 50: 6.5. Scan Conversion The following
Page 51 and 52: MB91460E Series The automatic inter
Page 53 and 54: ■ CLOCK SUPERVISOR (New Feature)
Page 55 and 56: 2.1. Clock Supervisor Control Regis
Page 57 and 58: 3. Block Diagram Clock Supervisor M
Page 59 and 60: MB91460E Series Figure 0-4 Timing D
Page 65 and 66: 4.3. Re-enabling the RC-oscillator
Page 67 and 68: MB91460E Series Figure 0-11 Timing
Page 69 and 70: Timing Diagram: Waking up from Sub
Page 71 and 72: 4.9. RTC mode (STOP mode with Real
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4.11. Check if reset was asserted b
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■ MB91460E Series DS705-00002-1v3
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2. Standby RAM MB91460E Series MB91
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3.3. EXTE: Shutdown recovery extern
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[bit 1] RTCF: Real Time Clock recov
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3.6. EXTLV1/2: Shutdown recovery ex
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4.1.3. Shutdown with Real Time Cloc
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4.1.8. External Interrupts: Level o
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4.3. Determining the Reset Source a
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4.5. I/O Behaviour in Shutdown Duri
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3. Programming model 3.1. Basic pro
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4.3. CCR (Condition Code Register)
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■ EMBEDDED PROGRAM/DATA MEMORY (F
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3.2. Flash access timing settings i
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4. Parallel Flash programming mode
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5. Poweron Sequence in parallel pro
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6.3. Security Vector FSV2 MB91460E
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■ MEMORY MAPS 1. MB91F467EA 00000
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Address 000000H 000004H 000008H Reg
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(Continued) Address 0000A0H Registe
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(Continued) Address 000180H Reserve
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(Continued) Address 000200H 000204H
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(Continued) Address 000348H 00034CH
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(Continued) Address 00048CH 000490H
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(Continued) Address + 0 + 1 Registe
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Address 000704H 000708H 00070CH 000
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(Continued) Address 000D80H 000D84H
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(Continued) Address 000E80H 000E84H
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(Continued) Address 002000H to 006F
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(Continued) Address 00C080H 00C084H
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(Continued) Address 00C1A0H 00C1A4H
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Address 00F09CH 00F0A0H 00F0A4H 00F
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32bit read/write dat[31:0] dat[31:0
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(Continued) Interrupt Decimal Inter
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(Continued) Interrupt Decimal Inter
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■ RECOMMENDED SETTINGS 1. PLL and
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MB91460E Series (Continued) Modulat
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MB91460E Series (Continued) Modulat
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(Continued) Modulation Degree (k) R
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“H” level average output curren
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2. Recommended operating conditions
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3. DC characteristics MB91460E Seri
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Parameter Symbol Analog inputleakag
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MB91460E Series 4. A/D converter ch
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Digital output 3FFH 3FEH 3FDH 004H
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5. Alarm comparator characteristics
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7. AC characteristics 7.1. Clock ti
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7.3. LIN-USART Timings at VDD5 = 3.
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7.4. I 2 C AC Timings at VDD5 = 3.0
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7.5. Free-run timer clock Input pul
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.7.4. Synchronous
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MB91460E Series 7.7.6. Asynchronous
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7.7.8. RDY waitcycle insertion Para
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7.7.10. Clock relationships MB91460
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MCLKO DACKX DEOP delayed DACKX dela
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.8.4. Synchronous
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MB91460E Series 7.8.6. Asynchronous
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7.8.8. RDY waitcycle insertion Para
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7.8.10. Clock relationships MCLKO
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MCLKO DACKX DEOP delayed DACKX dela
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■ PACKAGE DIMENSION 208-pin plast
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Version/ Date Ver. 0.8 2009-10-19 V
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■ CHANGES IN THIS EDITION DS705-0
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MEMO MB91460E Series DS705-00002-1v
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MB91460E Series DS705-00002-1v3-E 2
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FR60 MB91460E Series - Microcontrollers - Fujitsu

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