FR60 MB91460E Series - Microcontrollers - Fujitsu

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MB91460E Series 4.2. Recovery from shutdown mode The following factors are available to recover from the shutdown state: • Assert the reset signal at the INITX terminal for minimum 10 ms 12 • Input of a valid recovery request via an external interrupt terminal • Real Ttime Clock Interrupt (when RTC interrupt is enabled) • Hardware Watchdog reset (when HWWD is enabled in STOP mode) • Main Clock Supervisor reset (when Main oscillator is running and Main Clock Supervisor is enabled and recovery by HWWD is enabled) Shutdown state is released when a valid recovery factor is permitted. After the Shutdown state release, the device restarts with a settings initialization reset (INIT), just like power-up operation. Only the Real Time Clock, the Oscillation Stabilization settings in STCR register, and the recovery source flags in the Shutdown registers EXTF and SHDINT are not cleared. The internal restart sequence is as follows: 1. Resume the internal power supply. 2. Reset and assert the initialization reset (INIT). 3. Wait for oscillation stabilization. 4. Start the reset sequence. As the external interrupt source flags and the RTC flag are retained in EXTF and SHDINT registers, it is possible to determine whether it is power-up operation or recovery from shutdown state by checking the flags. 4.2.1. The Real Time Clock at Recovery from Shutdown In normal operation, the registers and settings of the Real Rime Clock are initialized by Software Reset (RST). At recovery from Shutdown, the RTC is not initialized: • The prescaler, second, minute and hour counters continue counting also during the recovery INIT state. • The clock selection for the RTC (by CSCFG.OSC1, CSCFG.OSC0) remains unchanged. • The RTC interrupt enable bits and interrupt flags (in WTCR and WTCE registers) remain unchanged. So at each recovery from Shutdown, the RTC continues running and the current time as well as the interrupt flags can be read from the RTC after recovery. Note: The Interrupt Control Register for RTC (ICR58), the Interrupt Level Mask (ILM) register as well as the Condition Code Register (CCR, containing the I-Flag) are cleared by the recovery INIT, so that all interrupt processing is disabled. If the software re-enables interrupt processing by setting ICR58, ILM and I-Flag, the software will process the pending RTC interrrupt immediately. 1. The minimum INTX=0 pulse length is determined by the time the main oscillator needs for stabilization. 2. Reset by INITX=0 will kill the ShutDown state and restart the device like at power-on. 88 DS705-00002-1v3-E
4.3. Determining the Reset Source after Shutdown MB91460E Series The recovery from Shutdown is followed by an Setting Initialization Reset (INIT). Because INIT is always followed by a Software Reset (RST), the CPU fetches the Mode- and Reset-Vectors and jumps to the Reset Vector, which is located in the Boot ROM. The following drawing shows how the Shutdown Control is located in the external INIT chain: INITX & Clock Supervisor Noise filter & Hardware Watchdog MM SM CPUF CL HWWDF RX1, RX0, INT7, INT6, RTCF CL CL INT3, INT2, INT1, INT0 Recovery flags External interrupts Low Volt CL Detection Shutdown Control No Shutdown Shutdown State Control Regs and State Machine CL Recover! Real Time Clock PR LINIT PR SINIT The following table lists the registers and flags for determination of the reset source, including Shutdown: Register Addr. 7 6 5 4 3 2 1 0 RSRR 480H 1 INIT HSTB WDOG ERST SRST LINIT WT1 WT0 EXTF 4D7H RX1 RX0 INT7 INT6 INT3 INT2 INT1 INT0 SHDINT 4DBH - - - - HWWDF HWWDE RTCF RTCE CSVCR 4ADH SCKS MM SM RCE MSVE SSVE SRST OUTE HWWD 4C7H - - - - CL - - CPUF 1. RSRR is read and cleared by the Boot ROM software. After Boot ROM, the content of RSRR can be found in CPU register R4[7:0] and in a variable in memory. Note: RSRR: Reset Source register EXTF: External shutdown recovery flags, see page 82 SHDINT: Hardware Watchdog/ Real Time Clock recovery flags, see page 80 CSVCR: CLock Supervisor Control / Status register HWWD: Hardware Watchdog register For details about RSRR, CSVCR and HWWD, please refer to the hardware manual. Recovery from Shutdown will set the INIT bit in RSRR register. Because the INIT bit can also be set by external INIT (low level at INITX pin), Clock Supervisor or Hardware Watchdog, the flags in EXTF, SHDINT, CSVCR and HWWD should be checked for determining the reset source. DS705-00002-1v3-E 89 & INIT LINIT Reset Source Register 1 INIT
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FUJITSU SEMICONDUCTOR DATA SHEET 32
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MB91460E Series (Continued) • Rea
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MB91460E Series Sound Generator 1 c
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MB91460E Series DS705-00002-1v3-E 7
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(Continued) Pin no. Pin name I/O 66
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Page 13 and 14:
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2. Power supply/Ground pins MB91460
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Type Circuit Remarks MB91460E Serie
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Type Circuit Remarks G Mask ROM and
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Type Circuit Remarks M CMOS level t
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(Continued) Example of using opposi
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■ NOTES ON DEBUGGER 1. Execution
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■ A/D CONVERTER / RANGE COMPARATO
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3. Block Diagram of A/D Converter T
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1. On MB91F467E, ADC1 does not exis
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• ADCS1 : Access: Half-word, Byte
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MB91460E Series [bit 9] STRT (Start
Page 37 and 38: 4.2. Common Data Register (ADCR1, A
Page 39 and 40: 4.5. A/D Channel Setting Register (
Page 41 and 42: 5.2. Range Comparator Registers The
Page 43 and 44: 5.2.3. Inverted Range Selection reg
Page 45 and 46: MB91460E Series The interrupt condi
Page 47 and 48: 6. Operation of A/D Converter MB914
Page 49 and 50: 6.5. Scan Conversion The following
Page 51 and 52: MB91460E Series The automatic inter
Page 53 and 54: ■ CLOCK SUPERVISOR (New Feature)
Page 55 and 56: 2.1. Clock Supervisor Control Regis
Page 57 and 58: 3. Block Diagram Clock Supervisor M
Page 59 and 60: MB91460E Series Figure 0-4 Timing D
Page 65 and 66: 4.3. Re-enabling the RC-oscillator
Page 67 and 68: MB91460E Series Figure 0-11 Timing
Page 69 and 70: Timing Diagram: Waking up from Sub
Page 71 and 72: 4.9. RTC mode (STOP mode with Real
Page 73 and 74: 4.11. Check if reset was asserted b
Page 75 and 76: ■ MB91460E Series DS705-00002-1v3
Page 77 and 78: 2. Standby RAM MB91460E Series MB91
Page 79 and 80: 3.3. EXTE: Shutdown recovery extern
Page 81 and 82: [bit 1] RTCF: Real Time Clock recov
Page 83 and 84: 3.6. EXTLV1/2: Shutdown recovery ex
Page 85 and 86: 4.1.3. Shutdown with Real Time Cloc
Page 87: 4.1.8. External Interrupts: Level o
Page 91 and 92: 4.5. I/O Behaviour in Shutdown Duri
Page 93 and 94: 3. Programming model 3.1. Basic pro
Page 95 and 96: 4.3. CCR (Condition Code Register)
Page 97 and 98: ■ EMBEDDED PROGRAM/DATA MEMORY (F
Page 99 and 100: 3.2. Flash access timing settings i
Page 101 and 102: 4. Parallel Flash programming mode
Page 103 and 104: 5. Poweron Sequence in parallel pro
Page 105 and 106: 6.3. Security Vector FSV2 MB91460E
Page 107 and 108: ■ MEMORY MAPS 1. MB91F467EA 00000
Page 109 and 110: Address 000000H 000004H 000008H Reg
Page 111 and 112: (Continued) Address 0000A0H Registe
Page 113 and 114: (Continued) Address 000180H Reserve
Page 115 and 116: (Continued) Address 000200H 000204H
Page 117 and 118: (Continued) Address 000348H 00034CH
Page 119 and 120: (Continued) Address 00048CH 000490H
Page 121 and 122: (Continued) Address + 0 + 1 Registe
Page 123 and 124: Address 000704H 000708H 00070CH 000
Page 125 and 126: (Continued) Address 000D80H 000D84H
Page 127 and 128: (Continued) Address 000E80H 000E84H
Page 129 and 130: (Continued) Address 002000H to 006F
Page 131 and 132: (Continued) Address 00C080H 00C084H
Page 133 and 134: (Continued) Address 00C1A0H 00C1A4H
Page 135 and 136: Address 00F09CH 00F0A0H 00F0A4H 00F
Page 137 and 138: 32bit read/write dat[31:0] dat[31:0
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(Continued) Interrupt Decimal Inter
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(Continued) Interrupt Decimal Inter
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■ RECOMMENDED SETTINGS 1. PLL and
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MB91460E Series (Continued) Modulat
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MB91460E Series (Continued) Modulat
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(Continued) Modulation Degree (k) R
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“H” level average output curren
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2. Recommended operating conditions
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3. DC characteristics MB91460E Seri
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Parameter Symbol Analog inputleakag
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MB91460E Series 4. A/D converter ch
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Digital output 3FFH 3FEH 3FDH 004H
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5. Alarm comparator characteristics
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7. AC characteristics 7.1. Clock ti
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7.3. LIN-USART Timings at VDD5 = 3.
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7.4. I 2 C AC Timings at VDD5 = 3.0
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7.5. Free-run timer clock Input pul
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.7.4. Synchronous
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MB91460E Series 7.7.6. Asynchronous
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7.7.8. RDY waitcycle insertion Para
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7.7.10. Clock relationships MB91460
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MCLKO DACKX DEOP delayed DACKX dela
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.8.4. Synchronous
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MB91460E Series 7.8.6. Asynchronous
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7.8.8. RDY waitcycle insertion Para
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7.8.10. Clock relationships MCLKO
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MCLKO DACKX DEOP delayed DACKX dela
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■ PACKAGE DIMENSION 208-pin plast
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Version/ Date Ver. 0.8 2009-10-19 V
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■ CHANGES IN THIS EDITION DS705-0
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MEMO MB91460E Series DS705-00002-1v
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MB91460E Series DS705-00002-1v3-E 2
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FR60 MB91460E Series - Microcontrollers - Fujitsu

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