FR60 MB91460E Series - Microcontrollers - Fujitsu

3.2. Flash access timing settings in CPU mode
MB91460E Series
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or
maximum clock modulation) for Flash read and write access.
3.2.1. Flash read timing settings (synchronous read)
Core clock (CLKB) ATD ALEH EQ WEXH WTC Remark
to 24 MHz 0 0 0 - 1
to 48 MHz 0 0 1 - 2
to 80 MHz 1 1 3 - 4
3.2.2. Flash write timing settings (synchronous write)
Core clock (CLKB) ATD ALEH EQ WEXH WTC Remark
to 32 MHz 1 - - 0 4
to 48 MHz 1 - - 0 5
to 64 MHz 1 - - 0 6
to 80 MHz 1 - - 0 7
DS705-00002-1v3-E 99