FR60 MB91460E Series - Microcontrollers - Fujitsu

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MB91460E Series 3.2. SHDE: Shutdown control register This register enables/disables the shutdown state as well as the Standby RAM. • SHDE : Address 0004D4H Access: Byte 7 6 5 4 3 2 1 0 SDENB - - - - - - RAMEN 0 X X X X X X 0 Initial value 1 retained X X X X X X 0 Initial value 1. Initial value after external pin INITX=0 or Shutdown Recovery 2 R/W - - - - - - R/W Attribute 2. Initial value after Software Reset (RST) [bit 7] SDENB : Shutdown enable SDENB Function 1 Enable shutdown state: On transition to STOP mode, the device enters Shutdown state. 0 Disable shutdown state: On transition to STOP mode, the device enters the normal STOP mode. [bit 6 to bit 1] Reserved bits • The read value is undefined. • Always write 0 to these bits. [bit 0] RAMEN : Standby RAM enable RAMEN Function 1 Enable the Standby RAM 1 : Read and write access to the Standby RAM is possible 0 Disable the Standby RAM: Read and write access to the Standby RAM is disabled. 1. The Standby RAM is located inside the address space of External Bus. If the Standby RAM is enabled, make sure that no chip select area of the External Bus overlaps the standby RAM area. Note: RAMEN is cleared by INIT and by Software Reset because the chip select control registers (CSER, ACR0-7, ASR0-7, AWR0-7) are initialized by the same conditions. After both kinds of reset, chip select CS0 is enabled to cover all addresses of external bus area, which would overlap the Standby RAM address space. Note: The bit RAMEN is written using CLKP, while the Standby RAM is accessed with CLKB. If CLKP is slower then CLKB, make sure to have some wait time (at least 2 CLKP periods) between setting of RAMEN and first RAM access. 78 DS705-00002-1v3-E
3.3. EXTE: Shutdown recovery external interrupt enable register MB91460E Series This register enables external interrupts as the source for recovering from the shutdown state. • EXTE : Address 0004D6H Access: Byte 7 6 5 4 3 2 1 0 RX1 RX0 INT7 INT6 INT3 INT2 INT1 INT0 0 0 0 0 0 0 0 0 Initial value 1 retained retained retained retained retained retained retained retained Initial value 1. Initial value after external pin INITX=0 or Shutdown Recovery 2 R/W R/W R/W R/W R/W R/W R/W R/W Attribute 2. Initial value after Software Reset (RST) Eight external interrupts that can be set as recovery sources are allocated to each bit, as shown in the table below: bit Pin No Pin Name 7 93 P32_2/RX1/INT9 6 91 P23_0/RX0/INT8 5 90 P24_7/SCL3/INT7 4 89 P24_6/SDA3/INT6 3 86 P24_3/INT3 2 85 P24_2/INT2 1 84 P24_1/INT1 0 83 P24_0/INT0 [bit 7 to bit 0] Interrupt enable bits Value Function 1 Enable recovery interrupt 0 Disable recovery interrupt • These bits can be read and written. • External pin INITX=0 or Shutdown recovery clear these bits. DS705-00002-1v3-E 79
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FUJITSU SEMICONDUCTOR DATA SHEET 32
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MB91460E Series (Continued) • Rea
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MB91460E Series Sound Generator 1 c
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MB91460E Series DS705-00002-1v3-E 7
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(Continued) Pin no. Pin name I/O 66
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2. Power supply/Ground pins MB91460
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Type Circuit Remarks MB91460E Serie
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Type Circuit Remarks G Mask ROM and
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Type Circuit Remarks M CMOS level t
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(Continued) Example of using opposi
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■ NOTES ON DEBUGGER 1. Execution
Page 27 and 28: ■ A/D CONVERTER / RANGE COMPARATO
Page 29 and 30: 3. Block Diagram of A/D Converter T
Page 31 and 32: 1. On MB91F467E, ADC1 does not exis
Page 33 and 34: • ADCS1 : Access: Half-word, Byte
Page 35 and 36: MB91460E Series [bit 9] STRT (Start
Page 37 and 38: 4.2. Common Data Register (ADCR1, A
Page 39 and 40: 4.5. A/D Channel Setting Register (
Page 41 and 42: 5.2. Range Comparator Registers The
Page 43 and 44: 5.2.3. Inverted Range Selection reg
Page 45 and 46: MB91460E Series The interrupt condi
Page 47 and 48: 6. Operation of A/D Converter MB914
Page 49 and 50: 6.5. Scan Conversion The following
Page 51 and 52: MB91460E Series The automatic inter
Page 53 and 54: ■ CLOCK SUPERVISOR (New Feature)
Page 55 and 56: 2.1. Clock Supervisor Control Regis
Page 57 and 58: 3. Block Diagram Clock Supervisor M
Page 59 and 60: MB91460E Series Figure 0-4 Timing D
Page 65 and 66: 4.3. Re-enabling the RC-oscillator
Page 67 and 68: MB91460E Series Figure 0-11 Timing
Page 69 and 70: Timing Diagram: Waking up from Sub
Page 71 and 72: 4.9. RTC mode (STOP mode with Real
Page 73 and 74: 4.11. Check if reset was asserted b
Page 75 and 76: ■ MB91460E Series DS705-00002-1v3
Page 77: 2. Standby RAM MB91460E Series MB91
Page 81 and 82: [bit 1] RTCF: Real Time Clock recov
Page 83 and 84: 3.6. EXTLV1/2: Shutdown recovery ex
Page 85 and 86: 4.1.3. Shutdown with Real Time Cloc
Page 87 and 88: 4.1.8. External Interrupts: Level o
Page 89 and 90: 4.3. Determining the Reset Source a
Page 91 and 92: 4.5. I/O Behaviour in Shutdown Duri
Page 93 and 94: 3. Programming model 3.1. Basic pro
Page 95 and 96: 4.3. CCR (Condition Code Register)
Page 97 and 98: ■ EMBEDDED PROGRAM/DATA MEMORY (F
Page 99 and 100: 3.2. Flash access timing settings i
Page 101 and 102: 4. Parallel Flash programming mode
Page 103 and 104: 5. Poweron Sequence in parallel pro
Page 105 and 106: 6.3. Security Vector FSV2 MB91460E
Page 107 and 108: ■ MEMORY MAPS 1. MB91F467EA 00000
Page 109 and 110: Address 000000H 000004H 000008H Reg
Page 111 and 112: (Continued) Address 0000A0H Registe
Page 113 and 114: (Continued) Address 000180H Reserve
Page 115 and 116: (Continued) Address 000200H 000204H
Page 117 and 118: (Continued) Address 000348H 00034CH
Page 119 and 120: (Continued) Address 00048CH 000490H
Page 121 and 122: (Continued) Address + 0 + 1 Registe
Page 123 and 124: Address 000704H 000708H 00070CH 000
Page 125 and 126: (Continued) Address 000D80H 000D84H
Page 127 and 128: (Continued) Address 000E80H 000E84H
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(Continued) Address 002000H to 006F
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(Continued) Address 00C080H 00C084H
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(Continued) Address 00C1A0H 00C1A4H
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Address 00F09CH 00F0A0H 00F0A4H 00F
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32bit read/write dat[31:0] dat[31:0
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(Continued) Interrupt Decimal Inter
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(Continued) Interrupt Decimal Inter
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■ RECOMMENDED SETTINGS 1. PLL and
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MB91460E Series (Continued) Modulat
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MB91460E Series (Continued) Modulat
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(Continued) Modulation Degree (k) R
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“H” level average output curren
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2. Recommended operating conditions
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3. DC characteristics MB91460E Seri
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Parameter Symbol Analog inputleakag
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MB91460E Series 4. A/D converter ch
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Digital output 3FFH 3FEH 3FDH 004H
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5. Alarm comparator characteristics
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7. AC characteristics 7.1. Clock ti
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7.3. LIN-USART Timings at VDD5 = 3.
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7.4. I 2 C AC Timings at VDD5 = 3.0
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7.5. Free-run timer clock Input pul
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.7.4. Synchronous
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MB91460E Series 7.7.6. Asynchronous
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7.7.8. RDY waitcycle insertion Para
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7.7.10. Clock relationships MB91460
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MCLKO DACKX DEOP delayed DACKX dela
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.8.4. Synchronous
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MB91460E Series 7.8.6. Asynchronous
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7.8.8. RDY waitcycle insertion Para
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7.8.10. Clock relationships MCLKO
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MCLKO DACKX DEOP delayed DACKX dela
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■ PACKAGE DIMENSION 208-pin plast
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Version/ Date Ver. 0.8 2009-10-19 V
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■ CHANGES IN THIS EDITION DS705-0
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MEMO MB91460E Series DS705-00002-1v
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MB91460E Series DS705-00002-1v3-E 2
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FR60 MB91460E Series - Microcontrollers - Fujitsu

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