FR60 MB91460E Series - Microcontrollers - Fujitsu

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MB91460E Series 4.2. Pin connections in parallel programming mode Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory’s interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of the signals to General Purpose Ports. Please see table below for signal mapping. In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash memory’s Auto Algorithms are available. Correspondence between MBM29LV400TC and Flash Memory Control Signals MBM29LV400TC External pins FR-CPU mode Flash memory mode MB91F467EA external pins Normal function Pin number ⎯ INITX ⎯ INITX 73 RESET ⎯ FRSTX P09_6 60 Comment ⎯ ⎯ MD_2 MD_2 70 Set to ‘1’ ⎯ ⎯ MD_1 MD_1 71 Set to ‘1’ ⎯ ⎯ MD_0 MD_0 72 Set to ‘1’ RY/BY FMCS:RDY bit RY/BYX P09_0 56 BYTE Internally fixed to ’H’ BYTEX P09_2 58 WE WEX P13_2 191 OE OEX P13_1 190 CE Internal control signal CEX P13_0 189 ⎯ + control via interface ATDIN P25_7 187 Set to ‘0’ ⎯ circuit EQIN P25_6 186 Set to ‘0’ ⎯ TESTX P09_3 59 Set to ‘1’ ⎯ RDYI P09_1 57 Set to ‘0’ A-1 FA0 P25_5 185 Set to ‘0’ A0 to A3 FA1 to FA4 P27_0 to P27_3 158 to 161 A4 to A7 FA5 to FA8 P27_4 to P27_7 164 to 167 A8 to A11 Internal address bus FA9 to FA12 P26_0 to P26_3 168 to 171 A12 to A15 FA13 to FA16 P26_4 to P26_7 174 to 177 A16 to A19 FA17 to FA20 P25_0 to P25_3 178 to 181 ⎯ FA21 P25_4 184 Set to ‘1’ DQ0 to DQ7 DQ0 to DQ7 P03_0 to P03_7 192 to 199 Internal data bus DQ8 to DQ15 DQ8 to DQ15 P02_0 to P02_7 200 to 207 102 DS705-00002-1v3-E
5. Poweron Sequence in parallel programming mode MB91460E Series The flash memory can be accessed in programming mode after a certain wait time, which is needed for Security Vector fetch: • Minimum wait time after VDD5/VDD5R power on: 2.76 ms • Minimum wait time after INITX rising: 1.0 ms 6. Flash Security 6.1. Vector addresses Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2) controlling the protection functions of the Flash Security Module: FSV1: 0x14:8000 BSV1: 0x14:8004 FSV2: 0x14:8008 BSV2: 0x14:800C 6.2. Security Vector FSV1 The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the individual write protection of the 8 Kbytes sectors. 6.2.1. FSV1 (bit31 to bit16) The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes. Explanation of the bits in the Flash Security Vector FSV1 [31:16] FSV1[31:19] FSV1[18] WriteProtection Level FSV1[17] Write Protection FSV1[16] Read Protection set all to “0” set to “0” set to “0” set to “1” set all to “0” set to “0” set to “1” set to “0” set all to “0” set to “0” set to “1” set to “1” set all to “0” set to “1” set to “0” set to “1” set all to “0” set to “1” set to “1” set to “0” set all to “0” set to “1” set to “1” set to “1” Flash Security Mode Read Protection (all device modes, except INTVEC mode MD[2:0] = “000”) Write Protection (all device modes, without exception) Read Protection (all device modes, except INTVEC mode MD[2:0] = “000”) and Write Protection (all device modes) Read Protection (all device modes, except INTVEC mode MD[2:0] = “000”) Write Protection (all device modes, except INTVEC mode MD[2:0] = “000”) Read Protection (all device modes, except INTVEC mode MD[2:0] = “000”) and Write Protection (all device modes except INTVEC mode MD[2:0] = “000”) DS705-00002-1v3-E 103
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FUJITSU SEMICONDUCTOR DATA SHEET 32
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MB91460E Series (Continued) • Rea
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MB91460E Series Sound Generator 1 c
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MB91460E Series DS705-00002-1v3-E 7
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(Continued) Pin no. Pin name I/O 66
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2. Power supply/Ground pins MB91460
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Type Circuit Remarks MB91460E Serie
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Type Circuit Remarks G Mask ROM and
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Type Circuit Remarks M CMOS level t
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(Continued) Example of using opposi
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■ NOTES ON DEBUGGER 1. Execution
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■ A/D CONVERTER / RANGE COMPARATO
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3. Block Diagram of A/D Converter T
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1. On MB91F467E, ADC1 does not exis
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• ADCS1 : Access: Half-word, Byte
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MB91460E Series [bit 9] STRT (Start
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4.2. Common Data Register (ADCR1, A
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4.5. A/D Channel Setting Register (
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5.2. Range Comparator Registers The
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5.2.3. Inverted Range Selection reg
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MB91460E Series The interrupt condi
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6. Operation of A/D Converter MB914
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6.5. Scan Conversion The following
Page 51 and 52: MB91460E Series The automatic inter
Page 53 and 54: ■ CLOCK SUPERVISOR (New Feature)
Page 55 and 56: 2.1. Clock Supervisor Control Regis
Page 57 and 58: 3. Block Diagram Clock Supervisor M
Page 59 and 60: MB91460E Series Figure 0-4 Timing D
Page 65 and 66: 4.3. Re-enabling the RC-oscillator
Page 67 and 68: MB91460E Series Figure 0-11 Timing
Page 69 and 70: Timing Diagram: Waking up from Sub
Page 71 and 72: 4.9. RTC mode (STOP mode with Real
Page 73 and 74: 4.11. Check if reset was asserted b
Page 75 and 76: ■ MB91460E Series DS705-00002-1v3
Page 77 and 78: 2. Standby RAM MB91460E Series MB91
Page 79 and 80: 3.3. EXTE: Shutdown recovery extern
Page 81 and 82: [bit 1] RTCF: Real Time Clock recov
Page 83 and 84: 3.6. EXTLV1/2: Shutdown recovery ex
Page 85 and 86: 4.1.3. Shutdown with Real Time Cloc
Page 87 and 88: 4.1.8. External Interrupts: Level o
Page 89 and 90: 4.3. Determining the Reset Source a
Page 91 and 92: 4.5. I/O Behaviour in Shutdown Duri
Page 93 and 94: 3. Programming model 3.1. Basic pro
Page 95 and 96: 4.3. CCR (Condition Code Register)
Page 97 and 98: ■ EMBEDDED PROGRAM/DATA MEMORY (F
Page 99 and 100: 3.2. Flash access timing settings i
Page 101: 4. Parallel Flash programming mode
Page 105 and 106: 6.3. Security Vector FSV2 MB91460E
Page 107 and 108: ■ MEMORY MAPS 1. MB91F467EA 00000
Page 109 and 110: Address 000000H 000004H 000008H Reg
Page 111 and 112: (Continued) Address 0000A0H Registe
Page 113 and 114: (Continued) Address 000180H Reserve
Page 115 and 116: (Continued) Address 000200H 000204H
Page 117 and 118: (Continued) Address 000348H 00034CH
Page 119 and 120: (Continued) Address 00048CH 000490H
Page 121 and 122: (Continued) Address + 0 + 1 Registe
Page 123 and 124: Address 000704H 000708H 00070CH 000
Page 125 and 126: (Continued) Address 000D80H 000D84H
Page 127 and 128: (Continued) Address 000E80H 000E84H
Page 129 and 130: (Continued) Address 002000H to 006F
Page 131 and 132: (Continued) Address 00C080H 00C084H
Page 133 and 134: (Continued) Address 00C1A0H 00C1A4H
Page 135 and 136: Address 00F09CH 00F0A0H 00F0A4H 00F
Page 137 and 138: 32bit read/write dat[31:0] dat[31:0
Page 139 and 140: (Continued) Interrupt Decimal Inter
Page 141 and 142: (Continued) Interrupt Decimal Inter
Page 143 and 144: ■ RECOMMENDED SETTINGS 1. PLL and
Page 145 and 146: MB91460E Series (Continued) Modulat
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Page 149 and 150: (Continued) Modulation Degree (k) R
Page 151 and 152: “H” level average output curren
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2. Recommended operating conditions
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3. DC characteristics MB91460E Seri
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Parameter Symbol Analog inputleakag
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MB91460E Series 4. A/D converter ch
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Digital output 3FFH 3FEH 3FDH 004H
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5. Alarm comparator characteristics
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7. AC characteristics 7.1. Clock ti
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7.3. LIN-USART Timings at VDD5 = 3.
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7.4. I 2 C AC Timings at VDD5 = 3.0
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7.5. Free-run timer clock Input pul
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.7.4. Synchronous
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MB91460E Series 7.7.6. Asynchronous
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7.7.8. RDY waitcycle insertion Para
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7.7.10. Clock relationships MB91460
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MCLKO DACKX DEOP delayed DACKX dela
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.8.4. Synchronous
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MB91460E Series 7.8.6. Asynchronous
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7.8.8. RDY waitcycle insertion Para
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7.8.10. Clock relationships MCLKO
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MCLKO DACKX DEOP delayed DACKX dela
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■ PACKAGE DIMENSION 208-pin plast
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Version/ Date Ver. 0.8 2009-10-19 V
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■ CHANGES IN THIS EDITION DS705-0
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MEMO MB91460E Series DS705-00002-1v
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MB91460E Series DS705-00002-1v3-E 2
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FR60 MB91460E Series - Microcontrollers - Fujitsu

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