FR60 MB91460E Series - Microcontrollers - Fujitsu

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MB91460E Series (Continued) Interrupt Decimal Interrupt number Hexadecimal Interrupt level *1 Interrupt vector *2 Setting Register Register address Offset Default Vector address DMA Resource number System reserved * 4 System reserved * 64 40 (ICR24) (458H) 2FCH 000FFEFCH ⎯ 4 65 41 2F8H 000FFEF8H ⎯ LIN-USART (FIFO) 4 RX 66 42 2F4H 000FFEF4H 10, 56 LIN-USART (FIFO) 4 TX LIN-USART (FIFO) 4 EoT 67 43 ICR25 459H 2F0H 000FFEF0H 11, 57 -- LIN-USART (FIFO) 5 RX 68 44 2ECH 000FFEECH 12, 58 LIN-USART (FIFO) 5 TX LIN-USART (FIFO) 5 EoT 69 45 ICR26 45AH 2E8H 000FFEE8H 13, 59 -- LIN-USART (FIFO) 6 RX 70 46 2E4H 000FFEE4H 60 LIN-USART (FIFO) 6 TX LIN-USART (FIFO) 6 EoT 71 47 ICR27 45BH 2E0H 000FFEE0H 61 -- LIN-USART (FIFO) 7 RX 72 48 2DCH 000FFEDCH 62 LIN-USART (FIFO) 7 TX LIN-USART (FIFO) 7 EoT 73 49 ICR28 45CH 2D8H 000FFED8H 63 -- I2C 0 / I2C 2 I 74 4A ICR29 45DH 2D4H 000FFED4H ⎯ 2C 3 75 4B 2D0H 000FFED0H ⎯ Reserved Reserved 76 77 4C 4D ICR30 45EH 2CCH 2C8H 000FFECCH 000FFEC8H 64 65 Reserved Reserved 78 79 4E 4F ICR31 45FH 2C4H 2C0H 000FFEC4H 000FFEC0H 66 67 Reserved Reserved 80 81 50 51 ICR32 460H 2BCH 2B8H 000FFEBCH 000FFEB8H 68 69 Reserved Reserved 82 83 52 53 ICR33 461H 2B4H 2B0H 000FFEB4H 000FFEB0H 70 71 Reserved Reserved 84 85 54 55 ICR34 462H 2ACH 2A8H 000FFEACH 000FFEA8H 72 73 Reserved Reserved 86 87 56 57 ICR35 463H 2A4H 2A0H 000FFEA4H 000FFEA0H 74 75 Reserved Reserved 88 89 58 59 ICR36 464H 29CH 298H 000FFE9CH 000FFE98H 76 77 Reserved Reserved 90 91 5A 5B ICR37 465H 294H 290H 000FFE94H 000FFE90H 78 79 (Continued) 140 DS705-00002-1v3-E
(Continued) Interrupt Decimal Interrupt number Hexadecimal MB91460E Series Interrupt level *1 Interrupt vector *2 Setting Register Register address Offset Default Vector address DMA Resource number Input Capture 0 Input Capture 1 92 93 5C 5D ICR38 466H 28CH 288H 000FFE8CH 000FFE88H 80 81 Input Capture 2 Input Capture 3 94 95 5E 5F ICR39 467H 284H 280H 000FFE84H 000FFE80H 82 83 Input Capture 4 Input Capture 5 96 97 60 61 ICR40 468H 27CH 278H 000FFE7CH 000FFE78H 84 85 Input Capture 6 Input Capture 7 98 99 62 63 ICR41 469H 274H 270H 000FFE74H 000FFE70H 86 87 Output Compare 0 Output Compare 1 100 101 64 65 ICR42 46AH 26CH 268H 000FFE6CH 000FFE68H 88 89 Output Compare 2 Output Compare 3 102 103 66 67 ICR43 46BH 264H 260H 000FFE64H 000FFE60H 90 91 Reserved Reserved 104 105 68 69 ICR44 46CH 25CH 258H 000FFE5CH 000FFE58H 92 93 Reserved Reserved 106 107 6A 6B ICR45 46DH 254H 250H 000FFE54H 000FFE50H 94 95 Sound Generator Phase Frequency Modulator 108 109 6C 6D ICR46 46EH 24CH 248H 000FFE4CH 000FFE48H ⎯ ⎯ Reserved 110 6E ICR47 * 3 Reserved 111 6F 46FH 244H 240H 000FFE44H 000FFE40H ⎯ ⎯ Reserved Reserved 112 113 70 71 ICR48 470H 23CH 238H 000FFE3CH 000FFE38H 15, 96 97 Reserved Reserved 114 115 72 73 ICR49 471H 234H 230H 000FFE34H 000FFE30H 98 99 PPG4 PPG5 116 117 74 75 ICR50 472H 22CH 228H 000FFE2CH 000FFE28H 100 101 PPG6 PPG7 118 119 76 77 ICR51 473H 224H 220H 000FFE24H 000FFE20H 102 103 PPG8 PPG9 120 121 78 79 ICR52 474H 21CH 218H 000FFE1CH 000FFE18H 104 105 PPG10 PPG11 122 123 7A 7B ICR53 475H 214H 210H 000FFE14H 000FFE10H 106 107 (Continued) DS705-00002-1v3-E 141
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FUJITSU SEMICONDUCTOR DATA SHEET 32
Page 3 and 4:
MB91460E Series (Continued) • Rea
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MB91460E Series Sound Generator 1 c
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MB91460E Series DS705-00002-1v3-E 7
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(Continued) Pin no. Pin name I/O 66
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Page 13 and 14:
Page 15 and 16:
2. Power supply/Ground pins MB91460
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Type Circuit Remarks MB91460E Serie
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Type Circuit Remarks G Mask ROM and
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Type Circuit Remarks M CMOS level t
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(Continued) Example of using opposi
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■ NOTES ON DEBUGGER 1. Execution
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■ A/D CONVERTER / RANGE COMPARATO
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3. Block Diagram of A/D Converter T
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1. On MB91F467E, ADC1 does not exis
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• ADCS1 : Access: Half-word, Byte
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MB91460E Series [bit 9] STRT (Start
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4.2. Common Data Register (ADCR1, A
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4.5. A/D Channel Setting Register (
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5.2. Range Comparator Registers The
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5.2.3. Inverted Range Selection reg
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MB91460E Series The interrupt condi
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6. Operation of A/D Converter MB914
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6.5. Scan Conversion The following
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MB91460E Series The automatic inter
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■ CLOCK SUPERVISOR (New Feature)
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2.1. Clock Supervisor Control Regis
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3. Block Diagram Clock Supervisor M
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MB91460E Series Figure 0-4 Timing D
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4.3. Re-enabling the RC-oscillator
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MB91460E Series Figure 0-11 Timing
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Timing Diagram: Waking up from Sub
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4.9. RTC mode (STOP mode with Real
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4.11. Check if reset was asserted b
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■ MB91460E Series DS705-00002-1v3
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2. Standby RAM MB91460E Series MB91
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3.3. EXTE: Shutdown recovery extern
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[bit 1] RTCF: Real Time Clock recov
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3.6. EXTLV1/2: Shutdown recovery ex
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4.1.3. Shutdown with Real Time Cloc
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4.1.8. External Interrupts: Level o
Page 89 and 90: 4.3. Determining the Reset Source a
Page 91 and 92: 4.5. I/O Behaviour in Shutdown Duri
Page 93 and 94: 3. Programming model 3.1. Basic pro
Page 95 and 96: 4.3. CCR (Condition Code Register)
Page 97 and 98: ■ EMBEDDED PROGRAM/DATA MEMORY (F
Page 99 and 100: 3.2. Flash access timing settings i
Page 101 and 102: 4. Parallel Flash programming mode
Page 103 and 104: 5. Poweron Sequence in parallel pro
Page 105 and 106: 6.3. Security Vector FSV2 MB91460E
Page 107 and 108: ■ MEMORY MAPS 1. MB91F467EA 00000
Page 109 and 110: Address 000000H 000004H 000008H Reg
Page 111 and 112: (Continued) Address 0000A0H Registe
Page 113 and 114: (Continued) Address 000180H Reserve
Page 115 and 116: (Continued) Address 000200H 000204H
Page 117 and 118: (Continued) Address 000348H 00034CH
Page 119 and 120: (Continued) Address 00048CH 000490H
Page 121 and 122: (Continued) Address + 0 + 1 Registe
Page 123 and 124: Address 000704H 000708H 00070CH 000
Page 125 and 126: (Continued) Address 000D80H 000D84H
Page 127 and 128: (Continued) Address 000E80H 000E84H
Page 129 and 130: (Continued) Address 002000H to 006F
Page 131 and 132: (Continued) Address 00C080H 00C084H
Page 133 and 134: (Continued) Address 00C1A0H 00C1A4H
Page 135 and 136: Address 00F09CH 00F0A0H 00F0A4H 00F
Page 137 and 138: 32bit read/write dat[31:0] dat[31:0
Page 139: (Continued) Interrupt Decimal Inter
Page 143 and 144: ■ RECOMMENDED SETTINGS 1. PLL and
Page 145 and 146: MB91460E Series (Continued) Modulat
Page 147 and 148: MB91460E Series (Continued) Modulat
Page 149 and 150: (Continued) Modulation Degree (k) R
Page 151 and 152: “H” level average output curren
Page 153 and 154: 2. Recommended operating conditions
Page 155 and 156: 3. DC characteristics MB91460E Seri
Page 157 and 158: Parameter Symbol Analog inputleakag
Page 159 and 160: MB91460E Series 4. A/D converter ch
Page 161 and 162: Digital output 3FFH 3FEH 3FDH 004H
Page 163 and 164: 5. Alarm comparator characteristics
Page 165 and 166: 7. AC characteristics 7.1. Clock ti
Page 167 and 168: 7.3. LIN-USART Timings at VDD5 = 3.
Page 169 and 170: 7.4. I 2 C AC Timings at VDD5 = 3.0
Page 171 and 172: 7.5. Free-run timer clock Input pul
Page 173 and 174: MCLKO CSXn delayed CSXn ASX ADDRESS
Page 175 and 176: MCLKO MCLKI CSXn WRXn (as byte enab
Page 177 and 178: MB91460E Series 7.7.4. Synchronous
Page 179 and 180: MB91460E Series 7.7.6. Asynchronous
Page 181 and 182: 7.7.8. RDY waitcycle insertion Para
Page 183 and 184: 7.7.10. Clock relationships MB91460
Page 185 and 186: MCLKO DACKX DEOP delayed DACKX dela
Page 187 and 188: MCLKO CSXn delayed CSXn ASX ADDRESS
Page 189 and 190: MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.8.4. Synchronous
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MB91460E Series 7.8.6. Asynchronous
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7.8.8. RDY waitcycle insertion Para
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7.8.10. Clock relationships MCLKO
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MCLKO DACKX DEOP delayed DACKX dela
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■ PACKAGE DIMENSION 208-pin plast
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Version/ Date Ver. 0.8 2009-10-19 V
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■ CHANGES IN THIS EDITION DS705-0
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MEMO MB91460E Series DS705-00002-1v
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MB91460E Series DS705-00002-1v3-E 2
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FR60 MB91460E Series - Microcontrollers - Fujitsu

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