FR60 MB91460E Series - Microcontrollers - Fujitsu

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MB91460E Series If a conversion is finished and the data of the previous conversion has not been read out before, previous data would be overwritten. To avoid this problem, the next conversion data is not stored in the data registers until the previous value has been read out (e.g. by DMA). A/D conversion halts during this time and the PAUS flag is set. A/D conversion restarts when the ADC interrupt flag ADCR1.INT is cleared. The register protection function depends on the conversion mode and the setting of ADCR2.INTE2: Mode INTE2 Function Single, Stop X Protection of ADCR Continous 0 Protection of ADCR 1 Protection of ADCD0...ADCD31 6.6.1. Protection of ADCD0...31 In continous mode with INTE2==1, PAUS is set when data of the start channel (set by ADSCH) is ready for writing to the registers, but IRQ2 (End of Scan interrupt) is already active. Example: Start channel =4, end channel=7, continous mode, ADCS1.INTE=0, ADCS2.INTE2=1 Start by CPU --> convert channel 4 + safe data to ADCD4, convert channel 5 + safe data to ADCD5, convert channel 6 + safe data to ADCD6, convert channel 7 + safe data to ADCD7 ---> End of Scan interrupt (IRQ2), convert channel 4 + set PAUS (protect ADCD4...7). After the CPU or DMA have read the data registers and cleared IRQ2, the scan conversion continues. 6.6.2. Protection of ADCR In the other modes or if INTE2==0, PAUS is set when data of any channel is ready for writing to the registers, but IRQ (End of Conversion) is active. Because in this mode the protection function is active after each single conversion, the ADCR register is protected. 7. ADC Interrupt Generation and DMA Access There are 2 ADC interrupt sources: End of Conversion and End of Scan. 7.1. End of Conversion The End of Conversion (EoC) interrupt is enabled by ADCS1.INTE bit and is compatible to the A/D convertes in old devices of MB91460 series. If EoC is enabled, it appeares after any conversion cycle. It is recommended to use DMA transfer to read out the data from ADCR. 7.2. End of Scan The End of Scan (EoS) interrupt is enabled by ADCS2.INTE2 bit. If EoS is enabled, it appeares after the conversion of the end channel, which is defined by the setting of ADECH register. If the End of Conversion interrupt is enabled in parallel, both interrupt bits are set. In this case it is recommended that the interrupt routine reads out ADCS2 register (containing mirrored bits of ADCS1[7:4]) to check where the interrupt comes from. 7.3. DMA Transfer DMA transfer can be triggered by End of Conversion interrupt or by End of Scan interrupt. The interrupts are assigned to separate DMA resource numbers (please refer to the Interrupt Vector Table). 50 DS705-00002-1v3-E
MB91460E Series The automatic interrupt clear after DMA transfer works for End of Conversion and for End of Scan separately. ■ HARDWARE WATCHDOG (Extension) This chapter describes a new feature of the Hardware Watchdog. For reference, please refer to chapter 21 Hardware Watchdog in the MB91460 series hardware manual. 1. Enabling the Hardware Watchdog in SLEEP and STOP State The Hardware Watchdog can now be enabled in SLEEP and STOP state by software. On old devices, the watchdog is cleared in SLEEP and STOP and restarts counting at the transition to RUN mode. Additionally, the restriction of MB91V460A about the settings ED1,ED0 = 01,10,11 has been removed. 1.1. HWWDE: Hardware watchdog timer duration register The Hardware Watchdog Timer Duration register changes like following: 7 6 5 4 3 2 1 0 Bit - - - STP_RUN - - ED1 ED0 X X X 0 X X 0 0 Initial value RX, W0 RX, W0 RX, W0 R, W1 RX, W0 RX, W0 R, W R, W Attribute • Bit7-5: Reserved bits. Always write 0 to these bits. • Bit4: STP_RUN (Run in SLEEP/STOP mode): - STP_RUN = 1 enables that the Hardware Watchdog continues running in SLEEP and STOP mode. The RC Oscillator will continue operation in SLEEP and STOP too. - STP_RUN = 0 (default) the the Hardware Watchdog is cleared in SLEEP and STOP mode. - STP_RUN can be set by CPU, but it cannot be cleared by the CPU - STP_RUN is cleared by software reset (RST) • Bit3-2: Reserved bits. Always write 0 to these bits. • Bit1-0: ED (Elongate watchdog duration). - These bits are cleared by software reset (RST) and can be written and read by CPU. 1.2. Caution ED1-0 Function 00 The watchdog period is 216 CLKRC cycles [initial setting] 01 The watchdog period is 217 CLKRC cycles 10 The watchdog period is 218 CLKRC cycles 11 The watchdog period is 219 CLKRC cycles The section “Caution” changes as follows: • Software disabling is not possible. The watchdog timer starts counting immediately after reset (release of INITX). Software cannot stop the counting. • Hardware disabling is only possible on the evaluation device MB91V460A and MB91FV460B. The watchdog timer can be permanently disabled by setting the corresponding jumper of the DS705-00002-1v3-E 51
Page 1 and 2: FUJITSU SEMICONDUCTOR DATA SHEET 32
Page 3 and 4: MB91460E Series (Continued) • Rea
Page 5 and 6: MB91460E Series Sound Generator 1 c
Page 7 and 8: MB91460E Series DS705-00002-1v3-E 7
Page 9 and 10: (Continued) Pin no. Pin name I/O 66
Page 15 and 16: 2. Power supply/Ground pins MB91460
Page 17 and 18: Type Circuit Remarks MB91460E Serie
Page 19 and 20: Type Circuit Remarks G Mask ROM and
Page 21 and 22: Type Circuit Remarks M CMOS level t
Page 23 and 24: (Continued) Example of using opposi
Page 25 and 26: ■ NOTES ON DEBUGGER 1. Execution
Page 27 and 28: ■ A/D CONVERTER / RANGE COMPARATO
Page 29 and 30: 3. Block Diagram of A/D Converter T
Page 31 and 32: 1. On MB91F467E, ADC1 does not exis
Page 33 and 34: • ADCS1 : Access: Half-word, Byte
Page 35 and 36: MB91460E Series [bit 9] STRT (Start
Page 37 and 38: 4.2. Common Data Register (ADCR1, A
Page 39 and 40: 4.5. A/D Channel Setting Register (
Page 41 and 42: 5.2. Range Comparator Registers The
Page 43 and 44: 5.2.3. Inverted Range Selection reg
Page 45 and 46: MB91460E Series The interrupt condi
Page 47 and 48: 6. Operation of A/D Converter MB914
Page 49: 6.5. Scan Conversion The following
Page 53 and 54: ■ CLOCK SUPERVISOR (New Feature)
Page 55 and 56: 2.1. Clock Supervisor Control Regis
Page 57 and 58: 3. Block Diagram Clock Supervisor M
Page 59 and 60: MB91460E Series Figure 0-4 Timing D
Page 65 and 66: 4.3. Re-enabling the RC-oscillator
Page 67 and 68: MB91460E Series Figure 0-11 Timing
Page 69 and 70: Timing Diagram: Waking up from Sub
Page 71 and 72: 4.9. RTC mode (STOP mode with Real
Page 73 and 74: 4.11. Check if reset was asserted b
Page 75 and 76: ■ MB91460E Series DS705-00002-1v3
Page 77 and 78: 2. Standby RAM MB91460E Series MB91
Page 79 and 80: 3.3. EXTE: Shutdown recovery extern
Page 81 and 82: [bit 1] RTCF: Real Time Clock recov
Page 83 and 84: 3.6. EXTLV1/2: Shutdown recovery ex
Page 85 and 86: 4.1.3. Shutdown with Real Time Cloc
Page 87 and 88: 4.1.8. External Interrupts: Level o
Page 89 and 90: 4.3. Determining the Reset Source a
Page 91 and 92: 4.5. I/O Behaviour in Shutdown Duri
Page 93 and 94: 3. Programming model 3.1. Basic pro
Page 95 and 96: 4.3. CCR (Condition Code Register)
Page 97 and 98: ■ EMBEDDED PROGRAM/DATA MEMORY (F
Page 99 and 100: 3.2. Flash access timing settings i
Page 101 and 102:
4. Parallel Flash programming mode
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5. Poweron Sequence in parallel pro
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6.3. Security Vector FSV2 MB91460E
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■ MEMORY MAPS 1. MB91F467EA 00000
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Address 000000H 000004H 000008H Reg
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(Continued) Address 0000A0H Registe
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(Continued) Address 000180H Reserve
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(Continued) Address 000200H 000204H
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(Continued) Address 000348H 00034CH
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(Continued) Address 00048CH 000490H
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(Continued) Address + 0 + 1 Registe
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Address 000704H 000708H 00070CH 000
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(Continued) Address 000D80H 000D84H
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(Continued) Address 000E80H 000E84H
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(Continued) Address 002000H to 006F
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(Continued) Address 00C080H 00C084H
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(Continued) Address 00C1A0H 00C1A4H
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Address 00F09CH 00F0A0H 00F0A4H 00F
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32bit read/write dat[31:0] dat[31:0
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(Continued) Interrupt Decimal Inter
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(Continued) Interrupt Decimal Inter
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■ RECOMMENDED SETTINGS 1. PLL and
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MB91460E Series (Continued) Modulat
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MB91460E Series (Continued) Modulat
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(Continued) Modulation Degree (k) R
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“H” level average output curren
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2. Recommended operating conditions
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3. DC characteristics MB91460E Seri
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Parameter Symbol Analog inputleakag
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MB91460E Series 4. A/D converter ch
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Digital output 3FFH 3FEH 3FDH 004H
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5. Alarm comparator characteristics
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7. AC characteristics 7.1. Clock ti
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7.3. LIN-USART Timings at VDD5 = 3.
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7.4. I 2 C AC Timings at VDD5 = 3.0
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7.5. Free-run timer clock Input pul
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.7.4. Synchronous
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MB91460E Series 7.7.6. Asynchronous
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7.7.8. RDY waitcycle insertion Para
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7.7.10. Clock relationships MB91460
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MCLKO DACKX DEOP delayed DACKX dela
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.8.4. Synchronous
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MB91460E Series 7.8.6. Asynchronous
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7.8.8. RDY waitcycle insertion Para
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7.8.10. Clock relationships MCLKO
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MCLKO DACKX DEOP delayed DACKX dela
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■ PACKAGE DIMENSION 208-pin plast
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Version/ Date Ver. 0.8 2009-10-19 V
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■ CHANGES IN THIS EDITION DS705-0
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MEMO MB91460E Series DS705-00002-1v
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MB91460E Series DS705-00002-1v3-E 2
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FR60 MB91460E Series - Microcontrollers - Fujitsu

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