FR60 MB91460E Series - Microcontrollers - Fujitsu

MB91460E Series
If the timeout is reached, the Hardware Watchdog generates INIT, which cancelles the Shutdown state and
forces recovery. The CPU will run on Main Oscillation after this recovery.
WARNING: If a Hardware Watchdog timeout INIT signal appeares just at the transition to Standby Mode, the device
may enter an unpredictable state. Always make sure that the hardware Watchdog has been cleared
just before entering Shutdown.
4.1.5. Clock Supervisor in Shutdown
The INITX pin, Clock Supervisor and Hardware Watchdog form the “external INIT chain”, like shown in the figure
in section “Determining the Reset Source after Shutdown” on page 89. The Shutdown control is part of this chain.
An INIT signal from the Clock Supervisor will pass the Hardware Watchdog and arrive at the same Shutdown
control input line as the INIT signal from Hardware Watchdog. Therefore, clock supervision in Shutdown mode
is only possible if the Hardware Watchdog is operating in parallel.
If the Hardware Watchdog is disabled in Shutdown mode, an INIT signal from the Clock Supervisor is ignored
in Shutdown.
The Clock Supervisor is enabled by default. In Shutdown mode, as long as the Main- and/or Sub-oscillator is
running and the RC clock is not stopped, the CSV is supervising the Main- or Sub-oscillator, respectively.
• The Clock Supervisor needs the RC clock, so set CSVCR.RCE=1, this is default setting.
• If the Main-oscillator is not stopped (STCR.OSCD1=0), the Main clock supervisor is running.
• If the Main-oscillator fails, the Main Clock Supervisor generates INIT, which can cancel the Shutdown state
and force recovery. The CPU runs on RC clock during and after the recovery.
• If the Sub-oscillator is not stopped (STCR.OSCD2=0), the Sub Clock Supervisor is running.
• If the Sub-oscillator fails, the Sub clock is switched to RC clock divided by 2. An INIT is not generated, and
the Real Time Clock continues running on on RC clock divided by 2, if RTC is enabled.
To disable the Clock Supervisor, clear the bits CSVCR.MSVE and CSVCR.SSVE.
4.1.6. Low Voltage Detection in Shutdown
Low Voltage Detection is not supported in Shutdown mode. Always set the Low Voltage Detection into power
down mode (LVDET.LVEPD=1, LVDET.LVIPD=1) before enabling Shutdown.
4.1.7. External Interrupts: Input Voltage Setting
The input voltages (CMOS-Schmitt, Automotive, TTL, CMOS-2) of the external interrupt lines are defined by the
setting of PILR and EPILR of the appropriate ports. The PILR and EPILR settings for the 8 external recovery
interrupt lines are maintained during Shutdown mode until they are cleared by the Software reset following the
Recovery INIT.
EPILR PILR Pin No Pin Name
EPILR23[2] PILR23[2] 93 P23_2/RX1/INT9
EPILR23[0] PILR23[0] 91 P23_0/RX0/INT8
EPILR24[7] PILR24[7] 90 P24_7/SCL3/INT7C
EPILR24[6] PILR24[6] 89 P24_6/SDA3/INT6D
EPILR24[3] PILR24[3] 86 P24_3/INT3
EPILR24[2] PILR24[2] 85 P24_2/INT2
EPILR24[1] PILR24[1] 84 P24_1/INT1
EPILR24[0] PILR24[0] 83 P24_0/INT0
86 DS705-00002-1v3-E