FR60 MB91460E Series - Microcontrollers - Fujitsu

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MB91460E Series ■ BLOCK DIAGRAM 1. MB91F467EA Flash-Cache 8 KByte Flash memory 1088 KByte (MB91F467EA) ID-RAM 48 KByte (MB91F467EA) Extended D-bus 32 Standby-RAM 16 KByte (MB91F467EA) Always ON Logic INT0 to INT3, INT6 to INT9 INT0 to INT10, INT12 to INT14 ICU0 to ICU7 OCU0 to OCU3 AIN0,AIN2,AIN3 BIN0,BIN2,BIN3 ZIN0,ZIN2,ZIN3 ALARM_0 DREQ0 DACKX0 DEOP0 DEOTX0 PFM FR60 CPU core I-bus 32 D-bus 32 Bus converter DMAC 5 channels Hardware Watchdog Real time clock Shutdown / Recovery Control External interrupt 14 channels Interrupt controller Input capture 8 channels Output compare 4 channels Up/down counter 3 channels PFM timer 1 channel Alarm comparator 1 channel D-RAM 64 KByte CAN 2 channels Bit search 32 16 bus adapter R-bus 16 External bus interface Clock modulator Clock supervisor Clock control BAAX WEX ASX RDX RX0 to RX1 TX0 to TX1 WRX0 to WRX3 BRQ MCLKE MCLKI BGRNTX CSX0 to CSX3,CSX6,CSX7 A0 to A25 D0 to D31 TTG8 to TTG11, TTG4/12 to TTG7/15 PPG4 to PPG15 TIN0 to TIN7 TOT0 to TOT3 CK2,CK4 to CK7 SIN2,SIN4 to SIN7 SOT2,SOT4 to SOT7 SCK2,SCK4 to SCK7 SDA0,SDA2,SDA3 SCL0,SCL2,SCL3 AN0 to AN7, AN16 to AN31 ATGX SMC1P0 to SMC1P5 SMC1M0 to SMC1M5 SMC2P0 to SMC2P5 SMC2M0 to SMC2M5 26 DS705-00002-1v3-E MCLKO Clock monitor MONCLK PPG timer 12 channels Reload timer 8 channels Free-run timer 8 channels LIN-USART 5 channels I C 3 channels 2 A/D converter 24 channels Stepper motor controller 6 channels Sound generator 1 channel Always ON Logic SGA SGO
■ A/D CONVERTER / RANGE COMPARATOR MB91460E Series The new A/D Converter with Range Comparator is available on MB91FV460B and some new flash devices and is backward compatible to the A/D converter used on older devices. Beside the Range Comparator, 32 separated result data registers, a second interrupt flag and a new behaviour regarding reading the ADCS0.ACH[5:0] bits have been implemented. There is one software incompatibility: Read-modify-write operation to the register ADCS0 is not allowed. See the description of the ADCS0.ACH[5:0] bits on 35ff. This chapter provides an overview of the A/D converter, describes the register structure and functions, and describes the operation of the A/D converter. 1. Overview of A/D Converter and A/D Range Comparator The A/D converter converts analog input voltages into digital values and provides the following features. Any ADC cannel can be assigned to one of 4 Range Comparators. 1.1. Features of the A/D converter: • Conversion time: minimum 1us per channel. • RC type successive approximation conversion with sample & hold circuit • 10-bit or 8-bit resolution • Program section analog input from 32 channels • 1 common result data register and 32 dedicated channel result data registers • Single conversion mode: Convert the specified channel(s) only once. • Continuous mode: Repeatedly convert the specified channels. • Scan conversion mode: Continuous conversion of multiple channels, programmable for up to 32 channels • Stop mode: Convert one channel, then temporarily halt until the next activation. (Enables synchronization of the conversion start timing.) • A/D conversion can be followed by an A/D conversion interrupt request to CPU. This interrupt, an option that is ideal for continuous processing can be used to start a DMA transfer of the results of A/D conversion to memory. • A/D conversion of all enabled channels (scan conversion) can be followed by an A/D End of Scan interrupt request to CPU. The data is stored into dedicated channel result registers, which can be read out using DMA transfer. • Conversion startup may be by software, external trigger (falling edge) or timer (rising edge). 1.2. Features of the A/D Range Comparator (RCO): • 4 conversion result Range Comparator channels, comparing the upper 8 bit of the conversion result with an upper and a lower threshold. The thresholds are programmable for the 4 comparators independendly. • Any ADC channel can be assigned to one of the 4 range comparators. • The comparision results will set “overflow” and “interrupt” flags per ADC channel, depending on the configuration. It is possible to configure the comparision for: - “out of range”: The flags are set if the A/D result is below the lower OR above the upper threshold. - “inside range”: The flags are set if the A/D result is above the lower AND below the upper threshold. • The configuration can be set individually per ADC channel. • Range comparision can be followed by an A/D Range Comparator interrupt request to CPU. DS705-00002-1v3-E 27
Page 1 and 2: FUJITSU SEMICONDUCTOR DATA SHEET 32
Page 3 and 4: MB91460E Series (Continued) • Rea
Page 5 and 6: MB91460E Series Sound Generator 1 c
Page 7 and 8: MB91460E Series DS705-00002-1v3-E 7
Page 9 and 10: (Continued) Pin no. Pin name I/O 66
Page 15 and 16: 2. Power supply/Ground pins MB91460
Page 17 and 18: Type Circuit Remarks MB91460E Serie
Page 19 and 20: Type Circuit Remarks G Mask ROM and
Page 21 and 22: Type Circuit Remarks M CMOS level t
Page 23 and 24: (Continued) Example of using opposi
Page 25: ■ NOTES ON DEBUGGER 1. Execution
Page 29 and 30: 3. Block Diagram of A/D Converter T
Page 31 and 32: 1. On MB91F467E, ADC1 does not exis
Page 33 and 34: • ADCS1 : Access: Half-word, Byte
Page 35 and 36: MB91460E Series [bit 9] STRT (Start
Page 37 and 38: 4.2. Common Data Register (ADCR1, A
Page 39 and 40: 4.5. A/D Channel Setting Register (
Page 41 and 42: 5.2. Range Comparator Registers The
Page 43 and 44: 5.2.3. Inverted Range Selection reg
Page 45 and 46: MB91460E Series The interrupt condi
Page 47 and 48: 6. Operation of A/D Converter MB914
Page 49 and 50: 6.5. Scan Conversion The following
Page 51 and 52: MB91460E Series The automatic inter
Page 53 and 54: ■ CLOCK SUPERVISOR (New Feature)
Page 55 and 56: 2.1. Clock Supervisor Control Regis
Page 57 and 58: 3. Block Diagram Clock Supervisor M
Page 59 and 60: MB91460E Series Figure 0-4 Timing D
Page 65 and 66: 4.3. Re-enabling the RC-oscillator
Page 67 and 68: MB91460E Series Figure 0-11 Timing
Page 69 and 70: Timing Diagram: Waking up from Sub
Page 71 and 72: 4.9. RTC mode (STOP mode with Real
Page 73 and 74: 4.11. Check if reset was asserted b
Page 75 and 76: ■ MB91460E Series DS705-00002-1v3
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2. Standby RAM MB91460E Series MB91
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3.3. EXTE: Shutdown recovery extern
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[bit 1] RTCF: Real Time Clock recov
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3.6. EXTLV1/2: Shutdown recovery ex
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4.1.3. Shutdown with Real Time Cloc
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4.1.8. External Interrupts: Level o
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4.3. Determining the Reset Source a
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4.5. I/O Behaviour in Shutdown Duri
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3. Programming model 3.1. Basic pro
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4.3. CCR (Condition Code Register)
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■ EMBEDDED PROGRAM/DATA MEMORY (F
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3.2. Flash access timing settings i
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4. Parallel Flash programming mode
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5. Poweron Sequence in parallel pro
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6.3. Security Vector FSV2 MB91460E
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■ MEMORY MAPS 1. MB91F467EA 00000
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Address 000000H 000004H 000008H Reg
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(Continued) Address 0000A0H Registe
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(Continued) Address 000180H Reserve
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(Continued) Address 000200H 000204H
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(Continued) Address 000348H 00034CH
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(Continued) Address 00048CH 000490H
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(Continued) Address + 0 + 1 Registe
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Address 000704H 000708H 00070CH 000
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(Continued) Address 000D80H 000D84H
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(Continued) Address 000E80H 000E84H
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(Continued) Address 002000H to 006F
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(Continued) Address 00C080H 00C084H
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(Continued) Address 00C1A0H 00C1A4H
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Address 00F09CH 00F0A0H 00F0A4H 00F
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32bit read/write dat[31:0] dat[31:0
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(Continued) Interrupt Decimal Inter
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(Continued) Interrupt Decimal Inter
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■ RECOMMENDED SETTINGS 1. PLL and
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MB91460E Series (Continued) Modulat
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MB91460E Series (Continued) Modulat
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(Continued) Modulation Degree (k) R
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“H” level average output curren
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2. Recommended operating conditions
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3. DC characteristics MB91460E Seri
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Parameter Symbol Analog inputleakag
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MB91460E Series 4. A/D converter ch
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Digital output 3FFH 3FEH 3FDH 004H
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5. Alarm comparator characteristics
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7. AC characteristics 7.1. Clock ti
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7.3. LIN-USART Timings at VDD5 = 3.
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7.4. I 2 C AC Timings at VDD5 = 3.0
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7.5. Free-run timer clock Input pul
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.7.4. Synchronous
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MB91460E Series 7.7.6. Asynchronous
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7.7.8. RDY waitcycle insertion Para
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7.7.10. Clock relationships MB91460
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MCLKO DACKX DEOP delayed DACKX dela
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.8.4. Synchronous
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MB91460E Series 7.8.6. Asynchronous
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7.8.8. RDY waitcycle insertion Para
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7.8.10. Clock relationships MCLKO
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MCLKO DACKX DEOP delayed DACKX dela
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■ PACKAGE DIMENSION 208-pin plast
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Version/ Date Ver. 0.8 2009-10-19 V
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■ CHANGES IN THIS EDITION DS705-0
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MEMO MB91460E Series DS705-00002-1v
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MB91460E Series DS705-00002-1v3-E 2
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FR60 MB91460E Series - Microcontrollers - Fujitsu

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