FR60 MB91460E Series - Microcontrollers - Fujitsu

6.5. Scan Conversion
The following figure shows the operation of A/D converter in Scan conversion mode
AN input
(1)
Scan start
channel
selection
Activation (2)
(trigger)
Result registers
ADCD0
ADCD1
ADCD2
ADCD3
End of Scan INT
PAUS
(3)
AN0
(4)
a, b, c
AN1 AN2 AN3
Sample hold
(5)
(6)
(7)
AN0 AN1 AN2 AN3
(8)
MB91460E Series
(1) Activation channel selection
(2) A/D activation (Trigger: Software trigger/Reload timer/External trigger)
(3) INT flag clear, PAUS flag clear
(4) AN0 conversion
a. Sample hold, conversion (conversion a + conversion b + conversion c)
b. Conversion end
c. Buffers the conversion value.
(5) AN1 conversion
(6) AN2 conversion
(7) AN3 conversion
(8) INT2 (End of Scan) flag is set, AN0 conversion starts
(9) Because INT2 has not been cleared yet, the ADC protects the result register of AN0
against overwriting and enters PAUSE state.
(10)INT2 flag cleared by DMA or by software, the ADC stores the result of AN0 and continues sampling AN1.
6.6. Protection of the ADC Channel Data Registers
There are 32 ADC result data registers, one register per channel. The registers are written by hardware at the
end of conversion of the attached channel. ADCD0 is attached to channel 0, ADCD31 is attached to channel 31.
The CPU can read the data registers any time.
DS705-00002-1v3-E 49
(9)
(10)
AN0 conversion value
AN1 conversion value
AN2 conversion value
AN3 conversion value
AN0 next conversion value
AN1 next value
AN0
AN2 next value