FR60 MB91460E Series - Microcontrollers - Fujitsu

MB91460E Series
4.4. Sampling Timer Setting Register (ADCT)
ADCT register controls the sampling time and comparison time of analog input. This register sets A/D conversion
time. Do not update value of this register during A/D conversion operation.
• ADCT1: Access: Word, Half-word, Byte
15 14 13 12 11 10 9 8 Bit
CT5 CT4 CT3 CT2 CT1 CT0 ST9 ST8
0 0 0 1 0 0 0 0 Initial value
R/W R/W R/W R/W R/W R/W R/W R/W Attribute
• ADCT0: Access: Word, Half-word, Byte
7 6 5 4 3 2 1 0 Bit
ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0
0 0 1 0 1 1 0 0 Initial value
R/W R/W R/W R/W R/W R/W R/W R/W Attribute
[bit 15 to 10] CT5-0 (A/D comparison time set)
These bits specify clock division of comparison time.
• Setting "000001" means one division (=CLKP).
• Do not set these bits "000000".
• Initialized these bits to "000100" by software reset (RST).
• Comparison time = CT value * CLKP cycle * 10 + (4 * CLKP)
• Do not set comparison time over 500 us.
[bit 9 to 0] ST9-0 (Analog input sampling time set)
These bits specify sampling time of analog input.
• Initialized these bits to "0000101100" by software reset (RST).
• Sampling time = ST value * CLKP cycle
• Do not set sampling time below 1.2 us when AVCC is below 4.5 V.
Necessary sampling time and ST value are calculated by following.
• Necessary sampling time (Tsamp) = (Rext + Rin) * Cin * 7
• ST9 to ST0 = Tsamp / CLKP cycle
ST has to be set that sampling time is over Tsamp.
Example: CLKP = 32MHz, AVCC >= 4.5V, Rext = 200K
Tsamp = ( 200 * 103 + 2.52 * 103 ) * 10.7 * 10-12 * 7 = 15.17 [us]
ST = 15.17-6 / 31.25-9 = 485.44
ST has to be set over 486D (111100110B).
Tsamp is decided by Rext. Thus conversion time should be considered together with Rext.
38 DS705-00002-1v3-E