section 7 - Index of

23 87 0I I I BUS'----v---JMR, GGR, OMR, AND SPAS A DESTINATION NOT USED LSBMR, GGR, OMR, AND SPASA SOURGEMR, GGR, OMR, AND SP-LG, LA, SR, SSH, AND SSLAS A DESTINATIONLG, LA, SR, SSH, AND SSLASASOURGE23 87 0ZERO FILLI I I BUS(a) 16 Bit23 0II BUS'--y----/NOT USED15LSBOFWORDJI123 1615 0I ZERO FIL~ I BUSLG, LA, SR, SSH, AND SSL(b) 8 BitFigure 6-6 Reading and Writing Control Registers6.3.2.3 Program Control RegistersThe 8-bit operating mode register (OMR) may be accessed as a word operand. However,not all eight bits are defined, and those that are defined will vary depending on theDSP56K family member. In general, undefined bits are written as "don't care" and read aszero.The 16-bit SR has the system mode register (MR) occupying the high-order eight bits andthe user condition code register (CCR) occupying the low-order eight bits. The SR maybe accessed as a word operand.