section 7 - Index of

-H- fast .............................. 7-26long ............................. 7-29Hardware DO Loop ................ 6-24, A-88 Interrupt Instruction Fetch ................ 7-24Hardware Interrupt ..................... 7-11 instructions preCeding ............... 7-25Hardware Interrupt Sources .............. 7-16 Interrupt Masks ........................ 5-12IROA ....... , .................... 7-16 Interrupt Priority Levels (IPL) ......... 5-6, 7-14IROB ............................ 7-16 Interrupt Priority Register ................ 7-14NMI ............................. 7-16 Interrupt Priority Structure ......... , ...... 7-12RESET .......................... 7-16 Interrupt Processing State ................ 7-10Hardware ResetI nterrupt Sources ....................... 7-16OnCE pins and .................... 10-5 hardware ......................... 7-16Helpline ........................... 11-16 other ............................ 7-22software .......................... 7-17trace ............................. 7-22Interrupt Types ........................ 7-12IIR Riter .............................. B-3 IPL .................................. 7-14ILLEGAL ............................ A-102 IROA ........ , ........ ' ........... , ... 5-6Illegal Instruction Interrupt (III) ............ 7-17 IRQB ................................. 5-6Immediate Data ..............•........ 6-14Immediate Short ....................... 6-14INC ................................ A-104Instruction Descriptions ................. A-21Instruction Encoding ................... A-311Instruction Format ................... 6-3, A-3Instruction Groups ..................... 6-20Instruction Guide ....................... A-3Instruction Pipeline .................. 5-6, 7-3restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 7-8Instruction Sequence Restrictions ...... : .A-305Instruction Syntax ....................... 6-3Instruction Timing ..................... A-294Instruction Timing Summary ............. A-301Instruction Timing Symbols ............... A-9Instructionsarithmetic ......................... 6-22bit manipulation . . . . . . . . . . . . . . . . . . . . 6-24logical ........................... 6-23loop ............................. 6-24move ........................ , ... 6-26program control . . . . . . . . . . . . . . . . . . . . 6-27Interruptfast ............................. 7-12hardware ......................... 7-11long ............................. 7-12restrictions . . . . . . . . . . . . . . . . . . . . . . . . 7-1 0sources .......................... 7-11Interrupt Arbitration ..................... 7-24Interrupt Control Pins .................... 2-6Interrupt Controller ..................... 7-24Interrupt Delay Possibilities .............. 7-25Interrupt Execution ..................... 7-26Jcc ................................ A-106JCLR .............................. A-110JMP ...................... '" ...... A-116JScc .............................. A-118JSCLR ............................ ' A-122JSET ............................. , A-130JSR .................. , ....... , .... A-136JSSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-138-1--J--L-LA .............................. 5-5, 5-17LC .............................. 5-5,5-17Level Sensitive .................... 5-6, 7-16Limit Bit ......................... 5-11 A-16Limiting (Saturation Arithmetic) .......... .' .. 3-9Linear Arithmetic ...................... .4-14Linear Modifier ........................ 4-16Lock, PLL, loss of ...................... 9-13Logic Unit ............................. 3-6Logical Instructions ..................... 6-23Long Interrupt ......................... 7-12Long Interrupt Execution ................. 7-29Long Word ............................. 6-5Loop Address (LA) Register .......... 5-5, 5-17Loop Counter (LC) Register .......... 5-5, 5-17Loop Flag Bit .......................... 5-13Loop Instructions ....................... 6-24Low Power Divider ...................... 9-3