section 7 - Index of

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I Document ID I Version Synopsis I Size Ifpfix.asm 2.0 Floating to fixed point conversion 3953fpfloat.asm 2.0 Fixed to floating point conversion 2053fpceil.asm 2.0 Floating point CEIL subroutine 1771fpfloor.asm 2.0 Floating point FLOOR subroutine 2119durbin.asm 1.0 Solution for LPC coefficients 5615durbin.hlp 1.0 Help file for DURBIN.ASM 2904fpfrac.asm 2.0 Floating point FRACTION subroutine 1862Functions:log2.asm 1.0 Log base 2 by polynomial 1118approxi mationlog2.hlp Help for log2.asm 719log2t.asm 1.0 Test program for log2.asm 1018log2nrm.asm 1.0 Normalizing base 2 logarithm macro 2262log2nrm.hlp Help for log2nrm.asm 676log2nrmt.asm 1.0 Test program for log2nrm.asm 1084exp2.asm 1.0 Exponential base 2 by polynomial 926approxi mationexp2.hlp Help for exp2.asm 759exp2t.asm 1.0 Test program for exp2.asm 1019sqrt1.asm 1.0 Square Root by polynomial 991approximation, 7 bit accuracysqrt1.hlp Help for sqrt1.asm 779sqrt1 t.asm 1.0 Test program for sqrt1.asm 1065sqrt2.asm 1.0 Square Root by polynomial 899approximation, 10 bit accuracysqrt2.hlp Help for sqrt2.asm 776sqrt2t.asm 1.0 Test program for sqrt2.asm 1031sqrt3.asm 1.0 Full precision Square Root Macro 1388sqrt3.hlp Help for sqrt3.asm 794sqrt3t.asm 1.0 Test program for sqrt3.asm 1053tlLasm 1.1 Linear table lookup/interpolation 3253routine for function generationtlLhlp 1.1 Help for tlLasm 1510
I Document ID I Version Synopsis I Size Ibingray.asm 1.0 Binary to G ray code conversion macro 601bingrayt.~sm 1.0 Test program for bingray.asm 991rand1.asm 1.1 Pseudo Random Sequence Generator 2446rand1.hlp Help for rand1.asm 704Lattice Filters:latfir1.asm 1.0 Lattice FIR Filter Macro 1156latfir1.hlp Help for latfir1.asm 6327latfir1 t.asm 1.0 Test program for latfir1.asm 1424latfir2.asm 1.0 Lattice FIR Filter Macro 1174(modified modulo count)latfir2.hlp Help for latfir2.asm 1295latfir2t.asm 1.0 Test program for latfir2.asm 1423latiir.asm 1.0 Lattice IIR Filter Macro 1257latiir.hlp Help for latiir.asm 6402latiirt.asm 1.0 Test program for latiir.asm 1407latgen.asm 1.0 Generalized Lattice FIRlIIR 1334Filter Macrolatgen.hlp Help for latgen.asm 5485latgent.asm 1.0 Test program for latgen.asm 1269latnrm.asm 1.0 Normalized Lattice IIR Filter Macro 1407latnrm.hlp Help for latnrm.asm 7475latnrmt.asm 1.0 Test program for latnrm.asm 1595Matrix Operations:matmul1.asm 1.0 [1 x3][3x3] =[1 x3] Matrix Multiplication 1817matmul1.hlp Help for matmul1.asm 527matmul2.asm 1.0 General Matrix Multiplication, C=AB 2650matmul2.hlp Help for matmul2.asm 780matmul3.asm 1.0 General Matrix Multiply-Accumulate, 2815C=AB+Qmatmul3.hlp 1.0 Help for matmul3.asm 865-
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DSP56K FAMILY INTRODUCTIONDSP56K CE
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Motorola reserves the right to make
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Table of Contents (Continued)Paragr
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ParagraphNumberTable of Contents (C
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FigureNumberList of Figures (Contin
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List of Tables (Continued)TablePage
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1.1 INTRODUCTIONThe DSP56K family i
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Fewer componentsStable, determinist
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Digital FilteringFinite Impulse Res
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architecture matches the shape of t
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• DSP56001 Compatibility - All me
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SECTION 2DSP56K CENTRAL ARCHITECTUR
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--I«a:w:ca.ffi~a. a.24-Bit 56KModu
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-rectly addressable registers: the
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3.1 DATA ARITHMETIC LOGIC UNITThis
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3.2.1 Data ALU Input Registers (X1,
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"""""" 24 BITS;:~:>~~::~~~:~:~:~:::
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3.2.4 Accumulator ShifterThe accumu
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Table 3-1 Limited Data ValuesDestin
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_--- N BITS ---_TWOS COMPLEMENT INT
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CASE I: IF AO < $800000 (1/2), THEN
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one instruction cycle. The ANDI ins
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3.5 DATA ALU PROGRAMMING MODELThe D
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4.1 ADDRESS GENERATION UNIT AND ADD
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!---LOWADDRESS ALU -----I~.j.I.....
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•••••••• _ ........
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4.4.1 Address Register Indirect Mod
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EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
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EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
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EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
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Table 4-2 Address Modifier SummaryM
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ADDRESS -f-_POINTERUPPER BOUNDARYiM
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EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
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oundary gives a 16-bit binary numbe
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4.4.2.4 Address-Modifier-Type Encod
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SECTION 5PROGRAM CONTROL UNIT-
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X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
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interruptible since they are fetche
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PROGRAM CONTROL UNIT-23 1615 023 16
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The GGR is a special purpose contro
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If S 1 =0 and SO=O (no scaling)then
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-23 876543210I * 1* JSO I * I Mel y
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5.4.5.1 Stack Pointer (Bits 0-3)The
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-DATA ARITHMETIC LOGIC UNITINPUT RE
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6.1 INSTRUCTION SET INTRODUCTIONThe
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shown in Figure 6-2. Most instructi
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23 87 0L...-I ___-'-I_---'I BUS~ LS
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The MR and CCR may be accessed indi
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6.3.4 Operand ReferencesThe DSP sep
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Some address register indirect mode
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EXAMPLE A: IMMEDIATE INTO 24-BIT RE
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EXAMPLE A: IMMEDIATE SHORT INTO AO,
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EXAMPLE A: MOVE P: $3200,XOBEFORE E
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Table 6-1 Addressing Modes SummaryA
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6.4.2 LogicallnstructlonsThe logica
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START OF LOOP1)SP+ 1 • SP; LA. SS
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OPCODE/OPERANDSPARALLEL MOVE EXAMPL
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SECTION 7PROCESSING STATES-
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Each instruction requires a minimum
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second instruction of the downloade
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The DO instruction is another instr
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SP and SSH/SSL register manipulatio
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7.3.1 Interrupt TypesThe DSP56K rel
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Table 7-2 Status Register Interrupt
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7.3.3 Interrupt SourcesInterrupts c
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interrupts makes it very useful for
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MAINPROGRAMFETCHESLONG INTERRUPTSER
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7.3.3.3 Other Interrupt SourcesOthe
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7.3.4 Interrupt ArbitrationInterrup
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7.3.7 Interrupt Instruction Executi
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MAINPROGRAMMEMORYINTERRUPT SYNCHRON
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MAINPROGRAMFETCHESINTERRUPTSYNCHRON
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MAINPROGRAMFAST INTERRUPTVECTORLONG
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MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
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7.5 WAIT PROCESSING STATEThe WAIT i
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The stop processing state halts all
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the first instruction fetch). If th
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RESET -----------------------------
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16 - BIT INTERNALADDRESS BUSESX ADD
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8.2.2.1 Address (AO-A15)These three
Page 177: SECTION 9PLL CLOCK OSCILLATOR-
Page 180 and 181: X MEMORYRAM/ROMEXPANSION24-Bit56KMo
Page 182 and 183: 23 22 21 20 19 18 17 16 15 14 13 12
Page 184 and 185: cleared. To enable rapid recovery w
Page 186 and 187: -CLVCCVCC for the CKOUT output. The
Page 188 and 189: 4. For all input frequencies which
Page 190 and 191: While the PLL is regaining lock, th
Page 193 and 194: 10.1 ON-CHIP EMULATION INTRODUCTION
Page 195 and 196: 10.2.2 Debug Serial Clock/Chip Stat
Page 197 and 198: 76543210I R/W I GO I EX I RS41 RS31
Page 199 and 200: shifted in (so a new command is ava
Page 201 and 202: 10.3.4.4 Software Debug Occurrence
Page 203 and 204: 10.4.4 Memory High Address Comparat
Page 205 and 206: 10.6.1 External Debug Request Durin
Page 207 and 208: PABCIRCULARBUFFERPOINTERDSCKDSOFigu
Page 209 and 210: are serially available to the exter
Page 211 and 212: k. ACKI. ClKm. Send command READ FI
Page 213 and 214: 19. ACK20. Send command READ GDB RE
Page 215 and 216: 10.11.6.1 Case 1: Return To The Pre
Page 217: SECTION 11ADDITIONAL SUPPORTDr. BuB
Page 220 and 221: The following is a partial list of
Page 222 and 223: • In-line assembler language code
Page 224 and 225: I Document 10 I Version Synopsis I
Page 232 and 233: 11.5 MOTOROLA DSP NEWSThe Motorola
Page 234 and 235: DIGITAL SIGNAL PROCESSINGAlan V. Op
Page 236 and 237: C Programming Language:Controls:. C
Page 238 and 239: Image Processing:DIGITAL IMAGE PROC
Page 240 and 241: LINEAR PREDICTION OF SPEECHJ. D. Ma
Page 243 and 244: A.1 APPENDIX A INTRODUCTIONThis app
Page 245 and 246: XnYnTable A-1 Instruction Descripti
Page 247 and 248: Table A-1 Instruction Description N
Page 249 and 250: Table A-1 Instruction Description N
Page 251 and 252: Table A-2 DSP56K Addressing ModesAd
Page 253 and 254: The address register indirect addre
Page 255 and 256: A.SCONDITION CODE COMPUTATION15 14
Page 257 and 258: S1 SO Scaling Mode Signed Integer P
Page 259 and 260: Table A-5 Condition Code Computatio
Page 261 and 262: A.7 INSTRUCTION DESCRIPTIONSThe fol
Page 263 and 264: ABSAbsolute ValueABSInstruction For
Page 265 and 266: ADC Add Long with Carry ADCresult.
Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
Page 269 and 270: ADDL Shift Left and Add Accumulator
Page 271 and 272: ADDR Shift Right and Add Accumulato
Page 273 and 274: ANDLogical ANDANDInstruction Format
Page 275 and 276: ANDIAND Immediate with Control Regi
Page 277 and 278: ASL Arithmetic Shift Accumulator Le
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ASR Arithmetic Shift Accumulator Ri
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BCHG Bit Test and Change BCHGExplan
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BCHGBit Test and ChangeBCHGInstruct
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BCHGBit Test and ChangeBCHGInstruct
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BCHG Bit Test and Change BCHGNotes:
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BCLR Bit Test and Clear BCLRExplana
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BClRBit Test and ClearBClRInstructi
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BClRBit Test and ClearBClRInstructi
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BClR Bit Test and Clear BClRNotes:
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BSET Bit Test and Set BSETExplanati
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BSETBit Test and SetBSETInstruction
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BSETBit Test and SetBSETInstruction
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BSET Bit Test and Set BSETNotes: If
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BTSTBit TestBTSTCondition Codes:115
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8TSTBit Test8TSTInstruction Format:
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8TSTBit Test8TSTInstruction Format:
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CLRClear AccumulatorCLRInstruction
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CMP Compare CMPCondition Codes:15 1
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CMPM Compare Magnitude CMPMConditio
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DEBUGEnter Debug ModeDEBUGOpcode:23
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DEBUGcc Enter Debug Mode Conditiona
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DEC Decrement by One DECInstruction
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DIV Divide Interation DIVThe DIV in
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DIV Divide Interation DIVNote that
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DIVInstruction Format:DIV S,DDivide
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DO Start Hardware Loop DOexecuted 6
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DOStart Hardware LoopDOAt LAOther R
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DOStart Hardware LoopDOInstruction
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DOStart Hardware LoopDOInstruction
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DO Start Hardware Loop DONotes: If
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ENDDO End Current DO Loop ENDDOExpl
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EOR Logical Exclusive OR EORInstruc
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ILLEGALIllegal Instruction Interrup
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INC Increment by One INCInstruction
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Jcc Jump Conditionally JccRestricti
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JccJump ConditionallyJccEffectiveAd
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JCLR Jump If Bit Clear JCLRRestrict
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JCLRJump If Bit ClearJCLRInstructio
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JCLR Jump If Bit Clear JCLRInstruct
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JMPJumpJMPInstruction Fields:xxx=12
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JSccJump to Subroutine Conditionall
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JScc Jump to Subroutine Conditional
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JSCLR Jump to Subroutine if Bit Cle
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JSCLRJump to Subroutine If Bit Clea
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JSCLRJump to Subroutine If Bit Clea
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JSCLR Jump to Subroutine If Bit Cle
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JSET Jump if Bit Set JSETRestrictio
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JSETJump if Bit SetJSETInstruction
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JSET Jump If Bit Set JSETInstructio
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JSR Jump to Subroutine JSRInstructi
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JSSET Jump to Subroutine if Bit Set
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JSSETJump to Subroutine if Bit SetJ
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JSSET Jump to Subroutine if Bit Set
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LSL Logical Shift Left LSLCondition
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LSR Logical Shift Right LSRConditio
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LUALoad Updated AddressLUACondition
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MAC Signed Multiply-Accumulate MACC
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MACSigned Multiply-AccumulateMACTim
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MACR Signed Multiply-Accumulate and
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MACR Signed MUltiply-Accumulate and
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MOVE Move Data MOVEExplanation of E
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MOVE Move Data MOVEWhen a 56-bit ac
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No Parallel Data MoveInstruction Fo
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I Immediate Short Data Move IExampl
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I Immediate Short Data Move IDDD d
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R Register to Register Data Move RE
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R Register to Register Data Move RI
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uAddress Register UpdateuInstructio
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X: X Memory Data Move X:Note:Due to
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X: X Memory Data Move X:S D DS,D d
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X: X Memory Data Move X:S D DS,D d
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X:R X Memory and Register Data Move
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Page 425 and 426:
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Y: Y Memory Data Move Y:Note: This
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Y: Y Memory Data Move Y:S D DS,D d
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Y: Y Memory Data Move Y:S D DS,D d
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R:V Register and V Memory Data Move
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R:V Register and Y Memory Data Move
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R:V Register and Y Memory Data Move
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L: Long Memory Data Move L:Example:
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L: Long Memory Data Move L:Instruct
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X: Y: xv Memory Data Move X: Y:Exam
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X: Y: xv Memory Data Move X: Y:S1 D
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MOVEC Move Control Register MOVECst
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MOVEC Move Control Register MOVECCo
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MOVECMove Control RegisterMOVECInst
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MOVEC Move Control Register MOVECTi
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MOVEM Move Program Memory MOVEMoper
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MOVEM Move Program Memory MOVEMInst
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MOVEMMove Program MemoryMOVEMInstru
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MOVEP Move Peripheral Data MOVEPist
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MOVEP Move Peripheral Data MOVEPCon
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MOVEP Move Peripheral Data MOVEPIns
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MOVEP Move Peripheral Data MOVEPIns
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MPY Signed Multiply MPYExplanation
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MPY Signed Multiply MPYInstruction
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MPYR Signed Multiply and Round MPYR
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MPYR Signed Multiply and Round MPYR
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NEGNegate AccumulatorNEGInstruction
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NOPNo OperationNOPInstruction Forma
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NORM Normalize Accumulator Iteratio
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NOTLogical ComplementNOTInstruction
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ORLogical Inclusive ORORInstruction
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ORI OR Immediate with Control Regis
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REP Repeat Next Instruction REPRest
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REPRepeat Next InstructionREPInstru
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REPRepeat Next InstructionREPInstru
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REP Repeat Next Instruction REPNote
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RESETReset On-Chip Peripheral Devic
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RND Round Accumulator RNDConvergent
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RNDRound AccumulatorRNDInstruction
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ROL Rotate Left ROLCondition Codes:
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ROR Rotate Right RORCondition Codes
Page 507 and 508:
RTIReturn from InterruptRTIConditio
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RTSReturn from SubroutineRTSInstruc
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sec Subtract Long with Carry secExp
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secSubtract Long with CarrysecInstr
Page 515 and 516:
STOPStop Instruction ProcessingSTOP
Page 517 and 518:
SUB Subtract SUBCondition Codes:S -
Page 519 and 520:
SUBL Shift Left and Subtract Accumu
Page 521 and 522:
SUBR Shift Right and Subtract Accum
Page 523 and 524:
SWISoftware InterruptSWICondition C
Page 525 and 526:
Tee Transfer Conditionally Teetion
Page 527 and 528:
Tee Transfer Conditionally TeeInstr
Page 529 and 530:
TFR Transfer Data ALU Register TFRC
Page 531 and 532:
TSTTest AccumulatorTSTInstruction F
Page 533 and 534:
WAIT Wait for Interrupt WAITConditi
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including the number of words per i
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5. Compute final results.Thus, base
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JLC (R2+N2)will requireand will exe
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Table A-6 Instruction Timing Summar
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Note that the "ap" term in Table A-
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Table A-14 Memory Access Timing Sum
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Other RestrictionsDO SSH,xxxxJSR to
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Immediately before MOVEC from SSH o
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A.9.S REP RestrictionsThe REP instr
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Table A-18 Triple-Bit Register Enco
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Table A-24 Program Control Unit Reg
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R: Register to Register Parallel Da
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JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
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JSSET#n,S,xxxx23 16 15 87 000001011
Page 563 and 564:
BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
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MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
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LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
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ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
Page 571 and 572:
Table A-28 Operation Code QQQ Decod
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Table A-30 Special Case #10 P E R C
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NEGD23 87 43 0DATA BUS MOVE FIELDLS
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ADDRS,D23 87 43 oDATA BUS MOVE FIEL
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lEI
Page 582 and 583:
Table 8-1 27-MHz Benchmark Results
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.*._---*-----*-------**-------....
Page 586 and 587:
;Latest Revision - September 30, 19
Page 588 and 589:
All coefficients are divided by 2:w
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Real input FFT based on Glenn Bergl
Page 592 and 593:
countountcountcountorg y:coefset 0d
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; Real-Valued FFT for MOTOROLA DSP5
Page 596 and 597:
; first group in the last passmove
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A Accumulator ....... ' ...........
Page 601 and 602:
-H- fast ..........................
Page 603 and 604:
PGND ..............................
Page 605 and 606:
DSP56K FAMILY INTRODUCTIONDSP56K CE
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