section 7 - Index of

8TST Bit Test 8TSTOperation:Assembler Syntax:D[n] -+ C; BTST #n,X:eaD[n] -+ C; BTST #n,X:aaD[n] -+ C; BTST #n,X:ppD[n] -+ C; BTST #n,Y:eaD[n] -+ C; BTST #n,Y:aaD[n] -+ C; BTST #n,Y:ppD[n] -+ C; BTST #n,DDescription: Test the nth bit of the destination operand D. The state of the nth bit isstored in the carry bit C of the condition code register. The bit to be tested is selected byan immediate bit number from 0-23. This instruction is useful for performing serial to parallelconversion when used with the appropriate rotate instructions. This instruction canuse all memory alterable addressing modes.Example:BTSTROL#$O,X:«$FFEEA;read SSI serial input flag IF1 into C bit;rotate carry bit C into LSB of A 1X:$FFEE 1-1Before Execution___-'-$o_o_oo_o2__---'After ExecutionX:$FFEE 1'--___ $_00_00_02 __--'SR~I ___ ~$_03_00 ____ ---'SRI'--___ ~$_03_01 ____ --'Explanation of Example: Prior to execution, the 24-bit X location X:$FFEE (1/0 SSI statusregister) contains the value $000002. The execution of the BTST #$1,X:«$FFEEinstruction tests the state of the 1 st bit (serial input flag IF1) in X:$FFEE and sets thecarry bit C accordingly. This instruction sequence illustrates serial to parallel conversionusing the carry bit C and the 24-bit A1 register.