section 7 - Index of

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Image Processing:DIGITAL IMAGE PROCESSINGWilliam K. PrattNew York, NY: John Wiley and Sons, 1978DIGITAL IMAGE PROCESSING (Second Edition)Rafael C. Gonzales and Paul WintzReading, MA: Addison-Wesley Publishing Company, Inc., 1977DIGITAL IMAGE PROCESSING TECHNIQUESM. P. EkstromNew York, NY: Academic Press, Inc., 1984DIGITAL PICTURE PROCESSINGAzriel Rosenfeld and Avinash C. KakNew York, NY: Academic Press, Inc., 1982SCIENCE OF FRACTAL IMAGES, THEM. F. Barnsley, R. L. Devaney, B. B. Mandelbrot, H. O. Peitgen,D. Saupe, and R. F. VossNew York, NY: Springer-VerlagMotorola DSP Manuals:MOTOROLA DSP56000 LINKER/LIBRARIAN REFERENCE MANUALMotorola, Inc., 1991.MOTOROLA DSP56000 MACRO ASSEMBLER REFERENCE MANUALMotorola, Inc., 1991.MOTOROLA DSP56000 SIMULATOR REFERENCE MANUALMotorola, Inc., 1991.MOTOROLA DSP56000/DSP56001 USER'S MANUALMotorola, Inc.,1990.Numerical Methods:ALGORITHMS (THE CONSTRUCTION, PROOF, AND ANALYSIS OFPROGRAMS)P. Berliout and P. BizardNew York, NY: John Wiley and Sons, 1986MATRIX COMPUTATIONSG. H. Golub and C. F. Van LoanJohn Hopkins Press, 1983
NUMERICAL RECIPES IN C - THE ART OF SCIENTIFIC PROGRAMMINGWilliam H. Press, Brian P. Flannery,Saul A. Teukolsky, and William T. VetterlingCambridge University Press, 1988NUMBER THEORY IN SCIENCE AND COMMUNICATIONManfred R. SchroederNew York, NY: Springer-Verlag, 1986Pattern Recognition:Speech:PATTERN CLASSIFICATION AND SCENE ANALYSISR. O. Duda and P. E. HartNew York, NY: John Wiley and Sons, 1973CLASSIFICATION ALGORITHMSMike JamesNew York, NY: Wiley-Interscience, 1985Spectral Analysis:STATISTICAL SPECTRAL ANALYSIS, A NON PROBABILISTIC THEORYWilliam A. GardnerEnglewood Cliffs, NJ: Prentice-Hall, Inc., 1988THE FAST FOURIER TRANSFORM AND ITS APPLICATIONSE. Oran BrighamEnglewood Cliffs, NJ: Prentice-Hall, Inc., 1988THE FAST FOURIER TRANSFORM AND ITS APPLICATIONSR. N. BracewellNew York, NY: McGraw-Hili Company, Inc., 1986ADAPTIVE FILTERS - STRUCTURES, ALGORITHMS, AND APPLICATIONSMichael L. Honig and David G. MesserschmittHigham, MA: Kluwer Academic Publishers, 1984DIGITAL CODING OF WAVEFORMSN. S. Jayant and P. NollEnglewood Cliffs, NJ: Prentice-Hall, Inc., 1984DIGITAL PROCESSING OF SPEECH SIGNALSLawrence R. Rabiner and R. W. SchaferEnglwood Cliffs, NJ: Prentice-Hall, Inc., 1978
Page 3 and 4:
DSP56K FAMILY INTRODUCTIONDSP56K CE
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Motorola reserves the right to make
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Table of Contents (Continued)Paragr
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ParagraphNumberTable of Contents (C
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FigureNumberList of Figures (Contin
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List of Tables (Continued)TablePage
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1.1 INTRODUCTIONThe DSP56K family i
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Fewer componentsStable, determinist
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Digital FilteringFinite Impulse Res
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architecture matches the shape of t
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• DSP56001 Compatibility - All me
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SECTION 2DSP56K CENTRAL ARCHITECTUR
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--I«a:w:ca.ffi~a. a.24-Bit 56KModu
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-rectly addressable registers: the
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3.1 DATA ARITHMETIC LOGIC UNITThis
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3.2.1 Data ALU Input Registers (X1,
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"""""" 24 BITS;:~:>~~::~~~:~:~:~:::
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3.2.4 Accumulator ShifterThe accumu
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Table 3-1 Limited Data ValuesDestin
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_--- N BITS ---_TWOS COMPLEMENT INT
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CASE I: IF AO < $800000 (1/2), THEN
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one instruction cycle. The ANDI ins
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3.5 DATA ALU PROGRAMMING MODELThe D
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4.1 ADDRESS GENERATION UNIT AND ADD
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!---LOWADDRESS ALU -----I~.j.I.....
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•••••••• _ ........
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4.4.1 Address Register Indirect Mod
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EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
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EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
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EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
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Table 4-2 Address Modifier SummaryM
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ADDRESS -f-_POINTERUPPER BOUNDARYiM
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EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
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oundary gives a 16-bit binary numbe
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4.4.2.4 Address-Modifier-Type Encod
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SECTION 5PROGRAM CONTROL UNIT-
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X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
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interruptible since they are fetche
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PROGRAM CONTROL UNIT-23 1615 023 16
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The GGR is a special purpose contro
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If S 1 =0 and SO=O (no scaling)then
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-23 876543210I * 1* JSO I * I Mel y
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5.4.5.1 Stack Pointer (Bits 0-3)The
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-DATA ARITHMETIC LOGIC UNITINPUT RE
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6.1 INSTRUCTION SET INTRODUCTIONThe
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shown in Figure 6-2. Most instructi
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23 87 0L...-I ___-'-I_---'I BUS~ LS
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The MR and CCR may be accessed indi
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6.3.4 Operand ReferencesThe DSP sep
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Some address register indirect mode
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EXAMPLE A: IMMEDIATE INTO 24-BIT RE
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EXAMPLE A: IMMEDIATE SHORT INTO AO,
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EXAMPLE A: MOVE P: $3200,XOBEFORE E
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Table 6-1 Addressing Modes SummaryA
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6.4.2 LogicallnstructlonsThe logica
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START OF LOOP1)SP+ 1 • SP; LA. SS
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OPCODE/OPERANDSPARALLEL MOVE EXAMPL
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SECTION 7PROCESSING STATES-
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Each instruction requires a minimum
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second instruction of the downloade
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The DO instruction is another instr
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SP and SSH/SSL register manipulatio
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7.3.1 Interrupt TypesThe DSP56K rel
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Table 7-2 Status Register Interrupt
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7.3.3 Interrupt SourcesInterrupts c
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interrupts makes it very useful for
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MAINPROGRAMFETCHESLONG INTERRUPTSER
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7.3.3.3 Other Interrupt SourcesOthe
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7.3.4 Interrupt ArbitrationInterrup
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7.3.7 Interrupt Instruction Executi
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MAINPROGRAMMEMORYINTERRUPT SYNCHRON
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MAINPROGRAMFETCHESINTERRUPTSYNCHRON
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MAINPROGRAMFAST INTERRUPTVECTORLONG
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MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
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7.5 WAIT PROCESSING STATEThe WAIT i
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The stop processing state halts all
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the first instruction fetch). If th
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RESET -----------------------------
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16 - BIT INTERNALADDRESS BUSESX ADD
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8.2.2.1 Address (AO-A15)These three
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SECTION 9PLL CLOCK OSCILLATOR-
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X MEMORYRAM/ROMEXPANSION24-Bit56KMo
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23 22 21 20 19 18 17 16 15 14 13 12
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cleared. To enable rapid recovery w
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-CLVCCVCC for the CKOUT output. The
Page 188 and 189: 4. For all input frequencies which
Page 190 and 191: While the PLL is regaining lock, th
Page 193 and 194: 10.1 ON-CHIP EMULATION INTRODUCTION
Page 195 and 196: 10.2.2 Debug Serial Clock/Chip Stat
Page 197 and 198: 76543210I R/W I GO I EX I RS41 RS31
Page 199 and 200: shifted in (so a new command is ava
Page 201 and 202: 10.3.4.4 Software Debug Occurrence
Page 203 and 204: 10.4.4 Memory High Address Comparat
Page 205 and 206: 10.6.1 External Debug Request Durin
Page 207 and 208: PABCIRCULARBUFFERPOINTERDSCKDSOFigu
Page 209 and 210: are serially available to the exter
Page 211 and 212: k. ACKI. ClKm. Send command READ FI
Page 213 and 214: 19. ACK20. Send command READ GDB RE
Page 215 and 216: 10.11.6.1 Case 1: Return To The Pre
Page 217: SECTION 11ADDITIONAL SUPPORTDr. BuB
Page 220 and 221: The following is a partial list of
Page 222 and 223: • In-line assembler language code
Page 224 and 225: I Document 10 I Version Synopsis I
Page 228 and 229: I Document ID I Version Synopsis I
Page 232 and 233: 11.5 MOTOROLA DSP NEWSThe Motorola
Page 234 and 235: DIGITAL SIGNAL PROCESSINGAlan V. Op
Page 236 and 237: C Programming Language:Controls:. C
Page 240 and 241: LINEAR PREDICTION OF SPEECHJ. D. Ma
Page 243 and 244: A.1 APPENDIX A INTRODUCTIONThis app
Page 245 and 246: XnYnTable A-1 Instruction Descripti
Page 247 and 248: Table A-1 Instruction Description N
Page 249 and 250: Table A-1 Instruction Description N
Page 251 and 252: Table A-2 DSP56K Addressing ModesAd
Page 253 and 254: The address register indirect addre
Page 255 and 256: A.SCONDITION CODE COMPUTATION15 14
Page 257 and 258: S1 SO Scaling Mode Signed Integer P
Page 259 and 260: Table A-5 Condition Code Computatio
Page 261 and 262: A.7 INSTRUCTION DESCRIPTIONSThe fol
Page 263 and 264: ABSAbsolute ValueABSInstruction For
Page 265 and 266: ADC Add Long with Carry ADCresult.
Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
Page 269 and 270: ADDL Shift Left and Add Accumulator
Page 271 and 272: ADDR Shift Right and Add Accumulato
Page 273 and 274: ANDLogical ANDANDInstruction Format
Page 275 and 276: ANDIAND Immediate with Control Regi
Page 277 and 278: ASL Arithmetic Shift Accumulator Le
Page 279 and 280: ASR Arithmetic Shift Accumulator Ri
Page 281 and 282: BCHG Bit Test and Change BCHGExplan
Page 283 and 284: BCHGBit Test and ChangeBCHGInstruct
Page 285 and 286: BCHGBit Test and ChangeBCHGInstruct
Page 287 and 288: BCHG Bit Test and Change BCHGNotes:
Page 289 and 290:
BCLR Bit Test and Clear BCLRExplana
Page 291 and 292:
BClRBit Test and ClearBClRInstructi
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BClRBit Test and ClearBClRInstructi
Page 295 and 296:
BClR Bit Test and Clear BClRNotes:
Page 297 and 298:
BSET Bit Test and Set BSETExplanati
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BSETBit Test and SetBSETInstruction
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BSETBit Test and SetBSETInstruction
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BSET Bit Test and Set BSETNotes: If
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BTSTBit TestBTSTCondition Codes:115
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8TSTBit Test8TSTInstruction Format:
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8TSTBit Test8TSTInstruction Format:
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CLRClear AccumulatorCLRInstruction
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CMP Compare CMPCondition Codes:15 1
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CMPM Compare Magnitude CMPMConditio
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DEBUGEnter Debug ModeDEBUGOpcode:23
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DEBUGcc Enter Debug Mode Conditiona
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DEC Decrement by One DECInstruction
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DIV Divide Interation DIVThe DIV in
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DIV Divide Interation DIVNote that
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DIVInstruction Format:DIV S,DDivide
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DO Start Hardware Loop DOexecuted 6
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DOStart Hardware LoopDOAt LAOther R
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DOStart Hardware LoopDOInstruction
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DOStart Hardware LoopDOInstruction
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DO Start Hardware Loop DONotes: If
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ENDDO End Current DO Loop ENDDOExpl
Page 341 and 342:
EOR Logical Exclusive OR EORInstruc
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ILLEGALIllegal Instruction Interrup
Page 345 and 346:
INC Increment by One INCInstruction
Page 347 and 348:
Jcc Jump Conditionally JccRestricti
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JccJump ConditionallyJccEffectiveAd
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JCLR Jump If Bit Clear JCLRRestrict
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JCLRJump If Bit ClearJCLRInstructio
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JCLR Jump If Bit Clear JCLRInstruct
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JMPJumpJMPInstruction Fields:xxx=12
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JSccJump to Subroutine Conditionall
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JScc Jump to Subroutine Conditional
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JSCLR Jump to Subroutine if Bit Cle
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JSCLRJump to Subroutine If Bit Clea
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JSCLRJump to Subroutine If Bit Clea
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JSCLR Jump to Subroutine If Bit Cle
Page 371 and 372:
JSET Jump if Bit Set JSETRestrictio
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JSETJump if Bit SetJSETInstruction
Page 375 and 376:
JSET Jump If Bit Set JSETInstructio
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JSR Jump to Subroutine JSRInstructi
Page 379 and 380:
JSSET Jump to Subroutine if Bit Set
Page 381 and 382:
JSSETJump to Subroutine if Bit SetJ
Page 383 and 384:
JSSET Jump to Subroutine if Bit Set
Page 385 and 386:
LSL Logical Shift Left LSLCondition
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LSR Logical Shift Right LSRConditio
Page 389 and 390:
LUALoad Updated AddressLUACondition
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MAC Signed Multiply-Accumulate MACC
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MACSigned Multiply-AccumulateMACTim
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MACR Signed Multiply-Accumulate and
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MACR Signed MUltiply-Accumulate and
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MOVE Move Data MOVEExplanation of E
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MOVE Move Data MOVEWhen a 56-bit ac
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No Parallel Data MoveInstruction Fo
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I Immediate Short Data Move IExampl
Page 407 and 408:
I Immediate Short Data Move IDDD d
Page 409 and 410:
R Register to Register Data Move RE
Page 411 and 412:
R Register to Register Data Move RI
Page 413 and 414:
uAddress Register UpdateuInstructio
Page 415 and 416:
X: X Memory Data Move X:Note:Due to
Page 417 and 418:
X: X Memory Data Move X:S D DS,D d
Page 419 and 420:
X: X Memory Data Move X:S D DS,D d
Page 421 and 422:
X:R X Memory and Register Data Move
Page 423 and 424:
Page 425 and 426:
Page 427 and 428:
Y: Y Memory Data Move Y:Note: This
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Y: Y Memory Data Move Y:S D DS,D d
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Y: Y Memory Data Move Y:S D DS,D d
Page 433 and 434:
R:V Register and V Memory Data Move
Page 435 and 436:
R:V Register and Y Memory Data Move
Page 437 and 438:
R:V Register and Y Memory Data Move
Page 439 and 440:
L: Long Memory Data Move L:Example:
Page 441 and 442:
L: Long Memory Data Move L:Instruct
Page 443 and 444:
X: Y: xv Memory Data Move X: Y:Exam
Page 445 and 446:
X: Y: xv Memory Data Move X: Y:S1 D
Page 447 and 448:
MOVEC Move Control Register MOVECst
Page 449 and 450:
MOVEC Move Control Register MOVECCo
Page 451 and 452:
MOVECMove Control RegisterMOVECInst
Page 453 and 454:
MOVEC Move Control Register MOVECTi
Page 455 and 456:
MOVEM Move Program Memory MOVEMoper
Page 457 and 458:
MOVEM Move Program Memory MOVEMInst
Page 459 and 460:
MOVEMMove Program MemoryMOVEMInstru
Page 461 and 462:
MOVEP Move Peripheral Data MOVEPist
Page 463 and 464:
MOVEP Move Peripheral Data MOVEPCon
Page 465 and 466:
MOVEP Move Peripheral Data MOVEPIns
Page 467 and 468:
MOVEP Move Peripheral Data MOVEPIns
Page 469 and 470:
MPY Signed Multiply MPYExplanation
Page 471 and 472:
MPY Signed Multiply MPYInstruction
Page 473 and 474:
MPYR Signed Multiply and Round MPYR
Page 475 and 476:
MPYR Signed Multiply and Round MPYR
Page 477 and 478:
NEGNegate AccumulatorNEGInstruction
Page 479 and 480:
NOPNo OperationNOPInstruction Forma
Page 481 and 482:
NORM Normalize Accumulator Iteratio
Page 483 and 484:
NOTLogical ComplementNOTInstruction
Page 485 and 486:
ORLogical Inclusive ORORInstruction
Page 487 and 488:
ORI OR Immediate with Control Regis
Page 489 and 490:
REP Repeat Next Instruction REPRest
Page 491 and 492:
REPRepeat Next InstructionREPInstru
Page 493 and 494:
REPRepeat Next InstructionREPInstru
Page 495 and 496:
REP Repeat Next Instruction REPNote
Page 497 and 498:
RESETReset On-Chip Peripheral Devic
Page 499 and 500:
RND Round Accumulator RNDConvergent
Page 501 and 502:
RNDRound AccumulatorRNDInstruction
Page 503 and 504:
ROL Rotate Left ROLCondition Codes:
Page 505 and 506:
ROR Rotate Right RORCondition Codes
Page 507 and 508:
RTIReturn from InterruptRTIConditio
Page 509 and 510:
RTSReturn from SubroutineRTSInstruc
Page 511 and 512:
sec Subtract Long with Carry secExp
Page 513 and 514:
secSubtract Long with CarrysecInstr
Page 515 and 516:
STOPStop Instruction ProcessingSTOP
Page 517 and 518:
SUB Subtract SUBCondition Codes:S -
Page 519 and 520:
SUBL Shift Left and Subtract Accumu
Page 521 and 522:
SUBR Shift Right and Subtract Accum
Page 523 and 524:
SWISoftware InterruptSWICondition C
Page 525 and 526:
Tee Transfer Conditionally Teetion
Page 527 and 528:
Tee Transfer Conditionally TeeInstr
Page 529 and 530:
TFR Transfer Data ALU Register TFRC
Page 531 and 532:
TSTTest AccumulatorTSTInstruction F
Page 533 and 534:
WAIT Wait for Interrupt WAITConditi
Page 535 and 536:
including the number of words per i
Page 537 and 538:
5. Compute final results.Thus, base
Page 539 and 540:
JLC (R2+N2)will requireand will exe
Page 541 and 542:
Table A-6 Instruction Timing Summar
Page 543 and 544:
Note that the "ap" term in Table A-
Page 545 and 546:
Table A-14 Memory Access Timing Sum
Page 547 and 548:
Other RestrictionsDO SSH,xxxxJSR to
Page 549 and 550:
Immediately before MOVEC from SSH o
Page 551 and 552:
A.9.S REP RestrictionsThe REP instr
Page 553 and 554:
Table A-18 Triple-Bit Register Enco
Page 555 and 556:
Table A-24 Program Control Unit Reg
Page 557 and 558:
R: Register to Register Parallel Da
Page 559 and 560:
JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
Page 561 and 562:
JSSET#n,S,xxxx23 16 15 87 000001011
Page 563 and 564:
BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
Page 565 and 566:
MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
Page 567 and 568:
LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
Page 569 and 570:
ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
Page 571 and 572:
Table A-28 Operation Code QQQ Decod
Page 573 and 574:
Table A-30 Special Case #10 P E R C
Page 575 and 576:
NEGD23 87 43 0DATA BUS MOVE FIELDLS
Page 577:
ADDRS,D23 87 43 oDATA BUS MOVE FIEL
Page 580 and 581:
lEI
Page 582 and 583:
Table 8-1 27-MHz Benchmark Results
Page 584 and 585:
.*._---*-----*-------**-------....
Page 586 and 587:
;Latest Revision - September 30, 19
Page 588 and 589:
All coefficients are divided by 2:w
Page 590 and 591:
Real input FFT based on Glenn Bergl
Page 592 and 593:
countountcountcountorg y:coefset 0d
Page 594 and 595:
; Real-Valued FFT for MOTOROLA DSP5
Page 596 and 597:
; first group in the last passmove
Page 599 and 600:
A Accumulator ....... ' ...........
Page 601 and 602:
-H- fast ..........................
Page 603 and 604:
PGND ..............................
Page 605 and 606:
DSP56K FAMILY INTRODUCTIONDSP56K CE
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