section 7 - Index of

BClR Bit Test and Clear BClRNotes: If A or 8 is specified as the destination operand, the following sequence of eventstakes place:1. The S bit is computed according to its definition (See Section A.S)2. The accumulator value is scaled according to the scaling mode bits SOand S1 in the status register (SR).3. If the accumulator extension is in use, the output of the shifter is limitedto the maximum positive or negative saturation constant, and the L bit isset.4. The resulting 24 bit value is placed back into A1 or 81. AO or 80 iscleared and the sign of A 1 or 81 is extended into A2 or 82.S. The bit test and clear is performed on A1 or 81, and the C bit is set if thebit tested is set.Timing: 4+mvb oscillator clock cyclesMemory: 1 +ea program words