section 7 - Index of

interruptible since they are fetched only once. A single-instruction DO loop can be usedin place of a REP instruction if interrupts must be allowed.5.3.3 Program Interrupt ControllerThe PIC receives all interrupt requests, arbitrates among them, and generates the interruptvector address.-Interrupts have a flexible priority structure with levels that can range from zero to three.Levels 0 (lowest level), 1, and 2 are maskable. Level 3 is the highest interrupt priority level(IPL) and is not maskable. Two interrupt mask bits in the SR reflect the current IPL andindicate the level needed for an interrupt source to interrupt the processor. Interruptscause the DSP to enter the exception processing state which is discussed fully in SEC­TION 7 - PROCESSING STATES.The four external interrupt sources include three external interrupt request inputs (IROA,IROS, and NMI) and the RESET pin. IROA and IROS can be either level sensitive or negativeedge triggered. The nonmaskable interrupt (NMI) is edge sensitive and is a level 3interrupt. MODNIROA, MODS/IROS, and MODC/NMI pins are sampled when RESET isdeasserted. The sampled values are stored in the operating mode register (OMR) bitsMA, MB, and MC, respectively (see Section 5.4.3 ,for information on the OMR). Only thefourth external interrupt, RESET, and Illegal Instruction have higher priority than NMI.The PIC also arbitrates between the different I/O peripherals. The currently selected peripheralsupplies the correct vector address to the PIC.5.3.4 Instruction Pipeline FormatThe program control unit uses a three-level pipe lined architecture in which concurrent instructionfetch, decode, and execution occur. This pipelined operation remains essentiallyhidden from the user and makes programming straightforward. The pipeline is illustratedin Figure 5-3, which shows the operations of each of the execution units and all initial conditionsnecessary to follow the execution of the instruction sequence shown in the figure.The pipeline is described in more detail in Section 7.2.1 Instruction Pipeline.The first instruction, 11, should be interpreted as follows: multiply the contents of XO by thecontents of VO, add the product to the contents already in accumulator A, round the resultto the "nearest even," store the result back in accumulator A, move the contents in X datamemory (pointed to by RO) into XO and postincrement RO, and move the contents in Vdata memory (pointed to by R4) into V1 and postincrement R4. The second instruction,12, should be interpreted as follows: clear accumulator A, move the contents in XO into thelocation in X data memory pointed to by RO and postincrement RO. Sefore the clear oper-