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DSP56K FAMILY INTRODUCTIONDSP56K CE
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Motorola reserves the right to make
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Table of Contents (Continued)Paragr
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ParagraphNumberTable of Contents (C
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FigureNumberList of Figures (Contin
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List of Tables (Continued)TablePage
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1.1 INTRODUCTIONThe DSP56K family i
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Fewer componentsStable, determinist
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Digital FilteringFinite Impulse Res
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architecture matches the shape of t
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• DSP56001 Compatibility - All me
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SECTION 2DSP56K CENTRAL ARCHITECTUR
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--I«a:w:ca.ffi~a. a.24-Bit 56KModu
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-rectly addressable registers: the
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3.1 DATA ARITHMETIC LOGIC UNITThis
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3.2.1 Data ALU Input Registers (X1,
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"""""" 24 BITS;:~:>~~::~~~:~:~:~:::
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3.2.4 Accumulator ShifterThe accumu
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Table 3-1 Limited Data ValuesDestin
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_--- N BITS ---_TWOS COMPLEMENT INT
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CASE I: IF AO < $800000 (1/2), THEN
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one instruction cycle. The ANDI ins
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3.5 DATA ALU PROGRAMMING MODELThe D
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4.1 ADDRESS GENERATION UNIT AND ADD
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!---LOWADDRESS ALU -----I~.j.I.....
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•••••••• _ ........
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4.4.1 Address Register Indirect Mod
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EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
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EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
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EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
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Table 4-2 Address Modifier SummaryM
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ADDRESS -f-_POINTERUPPER BOUNDARYiM
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EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
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- Page 79 and 80: 4.4.2.4 Address-Modifier-Type Encod
- Page 81: SECTION 5PROGRAM CONTROL UNIT-
- Page 84 and 85: X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
- Page 86 and 87: interruptible since they are fetche
- Page 88 and 89: PROGRAM CONTROL UNIT-23 1615 023 16
- Page 90 and 91: The GGR is a special purpose contro
- Page 92 and 93: If S 1 =0 and SO=O (no scaling)then
- Page 94 and 95: -23 876543210I * 1* JSO I * I Mel y
- Page 96 and 97: 5.4.5.1 Stack Pointer (Bits 0-3)The
- Page 98 and 99: -DATA ARITHMETIC LOGIC UNITINPUT RE
- Page 101 and 102: 6.1 INSTRUCTION SET INTRODUCTIONThe
- Page 103 and 104: shown in Figure 6-2. Most instructi
- Page 105 and 106: 23 87 0L...-I ___-'-I_---'I BUS~ LS
- Page 107 and 108: The MR and CCR may be accessed indi
- Page 109 and 110: 6.3.4 Operand ReferencesThe DSP sep
- Page 111 and 112: Some address register indirect mode
- Page 113 and 114: EXAMPLE A: IMMEDIATE INTO 24-BIT RE
- Page 115 and 116: EXAMPLE A: IMMEDIATE SHORT INTO AO,
- Page 117 and 118: EXAMPLE A: MOVE P: $3200,XOBEFORE E
- Page 119 and 120: Table 6-1 Addressing Modes SummaryA
- Page 121 and 122: 6.4.2 LogicallnstructlonsThe logica
- Page 123 and 124: START OF LOOP1)SP+ 1 • SP; LA. SS
- Page 125 and 126: OPCODE/OPERANDSPARALLEL MOVE EXAMPL
- Page 127: SECTION 7PROCESSING STATES-
- Page 131 and 132: Case 2: One of the more common sequ
- Page 133 and 134: Note 1: INST 3 may be executed at t
- Page 135 and 136: The restricted instructions at LA-2
- Page 137 and 138: the main uses of interrupts is to t
- Page 139 and 140: $0100MAINPROGRAMFAST INTERRUPT SERV
- Page 141 and 142: Table 7-3 Interrupt Priority Level
- Page 143 and 144: automatically when they are service
- Page 145 and 146: MAINPROGRAMFETCHESFAST INTERRUPTSER
- Page 147 and 148: ILLEGAL INSTRUCTION INTERRUPTRECOGN
- Page 149 and 150: MAINPROGRAMFETCHESTRACE INSTRUCTION
- Page 151 and 152: 7.3.6 . Instructions Preceding the
- Page 153 and 154: MAINPROGRAMMEMORYIINTERRUPT SYNCHRO
- Page 155 and 156: 6. The fast interrupt returns witho
- Page 157 and 158: MAINPROGRAMFAST INTERRUPTVECTORLONG
- Page 159 and 160: mented to one (see Figure 7-13). Du
- Page 161 and 162: MAINPROGRAMFETCHES~~I~-lI~~INTEARlP
- Page 163 and 164: INTERRUPT CONTROL CYCLE 1rINTERRUPT
- Page 165 and 166: IRQA ---------------.,FETCH n3 n4 -
- Page 167 and 168: the period of the first oscillator
- Page 171 and 172: 8.1 PORT A OVERVIEWPort A provides
- Page 173 and 174: e subdivided into three additional
- Page 175: WT) facility, which allows an exter
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9.1 PLL CLOCK OSCILLATOR INTRODUCTI
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The charge pump loop filter receive
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shows the programming of the DFO-DF
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Table 9-4 Clock Output Disable Bits
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9.4 PLL OPERATION CONSIDERATIONSThe
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chip clock. (Here, T3 is equal to t
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SECTION 10ON-CHIP EMULATION (OnCE)-
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...I~W:I:0...ffi~0...0...24-BitS6KM
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10.2.4 Debug Request Input (DR)The
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10.3.1.2 Exit Command (EX) Bit 5If
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When BC3-BCO=0011, program memory b
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OSCKPAB XAB YABOSO OSI~-- MEMORY BU
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To initiate the trace mode of opera
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the trace counter is decremented af
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the external command controller whe
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The external command controller act
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-After 24 bits have been received t
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10.11.4 Executing a Single-Word DSP
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PDS contains the second word of the
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11.1 USER SUPPORTUser support from
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the DSP56K family of processors•
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11.3.3 Support Integrated Circuits:
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I Document ID I Version Synopsis I
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I Document ID I Version Synopsis I
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I Document ID I Version Synopsis I
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I Document ID I Version Synopsis I
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11.12 TRAINING COURSES - (602) 897-
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ADAPTIVE SIGNAL PROCESSINGB. Widrow
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Graphics:CGM AND CGID. B. Arnold an
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NUMERICAL RECIPES IN C - THE ART OF
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APPENDIX AINSTRUCTION SET DETAILSAr
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word is optional, it is so indicate
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Table A-1 Instruction Description N
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Table A-1 Instruction Description N
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A.4 ADDRESSING MODESThe addressing
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Addressing ModeTable A-3 DSP56K Add
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Table A-4 Addressing Mode Modifier
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S (Scaling Bit)The scaling bit (S)
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C (Carry Bit)Set if a carry is gene
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The following notes apply to Table
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ABS Absolute Value ABSOperation:I D
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ACC Add Long with Carry ACCOperatio
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ADD Add ADDOperation:S+D-+D (parall
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ADDL Shift Left and Add Accumulator
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ADDR Shift Right and Add Accumulato
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AND Logical AND ANDOperation:S - 0[
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ANDIAND Immediate with Control Regi
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ASL Arithmetic Shift Accumulator Le
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ASR Arithmetic Shift Accumulator Ri
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BCHG Bit Test and Change BCHGOperat
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BCHGBit Test and ChangeBCHGFor othe
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BCHGBit Test and ChangeBCHGInstruct
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BCHGBit Test and Ch~ngeBCHGInstruct
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BCLR Bit Test and Clear BCLROperati
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BCLRBit Test and ClearBCLRFor other
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BCLRBit Test and ClearBCLRInstructi
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BCLRBit Test and ClearBCLRInstructi
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BSET Bit Test and Set BSElOperation
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BSElBit Test and SetBSElFor other d
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BSETBit Test and SetBSETInstruction
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BSETBit Test and SetBSETInstruction
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8TST Bit Test 8TSTOperation:Assembl
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BTSTBit TestBTSTInstruction Format:
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8TSTBit Test8TSTInstruction Format:
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CLR Clear Accumulator CLROperation:
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CMP Compare CMPOperation:Assembler
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CMPM Compare Magnitude CMPMOperatio
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DEBUG Enter Debug Mode DEB,UGOperat
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DEBUGcc Enter Debug Mode Conditiona
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DECDecrement by OneDECOperation:0-1
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DIV Divide Interation DIVOperation:
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DIV Divide Interation DIVExample: (
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DIV Divide Interatlon DIVA complete
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DOStart Hardware LoopDOOperation:As
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DO Start Hardware Loop DOmented by
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DOStart Hardware LoopDOExample:DO #
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DO Start Hardware Loop DOInstructio
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DO Start Hardware Loop DOInstructio
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ENDDO End Current DO Loop ENDDOOper
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EOR Logical Exclusive OR EOROperati
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ILLEGALIllegal Instruction Interrup
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INC Increment by One INCOperation:A
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JccJump ConditionallyJccOperation:I
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Jcc Jump Conditionally JccInstructi
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JCLR Jump If Bit Clear JCLROperatio
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JCLRJump if Bit ClearJCLRInstructio
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JCLRJump if Bit ClearJCLRInstructio
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JMPJumpJMPOperation:Oxxx --t PCea -
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JScc Jump to Subroutine Conditional
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JScc Jump to Subroutine Conditional
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JSCLR Jump to Subroutine If Bit Cle
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JSCLR Jump to Subroutine if Bit Cle
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JSCLRJump to Subroutine if Bit Clea
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JSCLR Jump to Subroutine if Bit Cle
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JSETJump If Bit SetJSETOperation:If
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JSETJump If Bit SetJSETInstruction
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JSETJump if Bit SetJSETInstruction
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JSR Jump to Subroutine JSROperation
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JSSET Jump to Subroutine if Bit Set
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JSSETJump to Subroutine If Bit SetJ
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JSSETJump to Subroutine If Bit SetJ
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LSL Logical ~hlft Left LSLOperation
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LSR Logical Shift Right LSROperatio
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LUALoad Updated AddressLUAOperation
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MAC Signed Multiply-Accumulate MACO
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MACSigned Multiply-AccumulateMACTim
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MACR Signed Multiply-Accumulate and
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MACR Signed Multiply-Accumulate and
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MOVE Move Data MOVEOperation:S~DAss
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MOVE Move Data MOVEParallel Move De
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No Parallel Data MoveOperation:Asse
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IImmediate Short Data MoveIOperatio
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IImmediate Short Data MoveIConditio
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RRegister to Register Data MoveROpe
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R Register to Register Data Move RC
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uAddress Register UpdateuOperation:
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X: X Memory Data Move X:Operation:A
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X: X Memory Data Move X:Instruction
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X: X Memory Data MoveX:Instruction
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X:RX Memory and Register Data MoveX
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X:R X Memory and Register Data Move
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X:R X Memory and Register Data Move
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Y: V Memory Data Move Y:Operation:A
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V: Y Memory Data Move V:Note: The M
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V: Y Memory Data MoveV:Instruction
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R:V Register and V Memory Data Move
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R:Y Register and Y Memory Data Move
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R:VRegister and V Memory Oata MoveR
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L: Long Memory Data Move L:Operatio
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L: Long Memory Data Move L:Instruct
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X: V: xv Memory Data Move X: V:Oper
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X: V: xv Memory Data Move X: V:Note
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MOVEC Move Control Register MOVECOp
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MOVEC Move Control Register MOVECA
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MOVECMove Control RegisterMOVECRegi
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MOVECMove Control RegisterMOVECInst
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MOVEMMove Program MemoryMOVEMOperat
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MOVEM Move Program Memory MOVEMExam
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MOVEM Move Program Memory MOVEMS D
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MOVEP Move Peripheral Data MOVEPOpe
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_______-----'MOVEP Move Peripheral
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MOVEPMove Peripheral DataMOVEPInstr
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MOVEPMove Peripheral DataMOVEPInstr
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MPY Signed Multiply MPYOperation:±
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MPY Signed Multiply MPYInstruction
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MPYR Signed Multiply and Round MPYR
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MPYR Signed Multiply and Round MPYR
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NEG Negate Accumulator NEGOperation
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NOP No Operation NOPOperation:PC+1-
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NORM Normalize Accumulator Iteratio
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NOT Logical Complement NOTOperation
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OR Logical Inclusive OR OROperation
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ORI OR Immediate with Control Regis
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REP Repeat Next Instruction REPOper
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REP Repeat Next Instruction REPExpl
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REPRepeat Next InstructionREPInstru
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REP Repeat Next Instruction REPInst
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RESETReset On-Chip Peripheral Devic
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RND Round Accumulator RNDOperation:
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RND Round Accumulator RNDCondition
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ROL Rotate Left ROLOperation:r47 24
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ROR Rotate Right ROROperation: c:c~
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RTI Return from Interrupt RTIOperat
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RTS Return from Subroutine RTSOpera
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SBC Subtract Long with Carry secOpe
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SBC Subtract Long with Carry SBCCon
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STOP Stop Instruction Processing ST
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SUB Subtract SUBOperation:O-S -4 D
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SUBL Shift Left and Subtract Accumu
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SUBR Shift Right and Subtract Accum
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SWI Software Interrupt SWIOperation
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Tee Transfer Conditionally TeeOpera
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Tee Transfer Conditionally TeeInstr
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TFR Transfer Data ALU Register TFRO
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TST Test Accumulator TSTOperation:A
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WAIT Wait for Interrupt WAITOperati
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A.a INSTRUCTION TIMINGThis section
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cycles that may be required over an
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additional (if any) instruction pro
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3. Evaluate the "ap" term using Tab
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Table A-7 Parallel Data Move Timing
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Table A-12 RTIIRTS Timing SummaryOp
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A.9.1 Restrictions Near the End of
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Immediately before ENDDOBCHG lA, lC
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Immediately before JSCLR from SSH o
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Section A.10.4 gives the encoding f
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Table A-20 Five-Bit Register Encodi
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A.10.2 Instruction Encoding for the
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A.10.3 Instruction Encoding for Ins
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JSETJSET#n,X:ea,xxxx#n,Y:ea,xxxx23
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BCLRBCLR#n,X:pp#n,Y:pp23I 0 0 0 016
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BCLR23#n,O0 0 0 0 1 016 15 871 o \
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DODOX:ea,exprV:ea,expr23 16 15 87 0
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MPYR (±)S,#n,DDEBUGccDEBUG23 16 15
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ILLEGALRTINOP23 16 15 87 0I 0 0 0 0
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Nonmultlply Instruction EncodingThe
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EORS,D23 87 43 0DATA BUS MOVE FIELD
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NOTD23 87 43 0DATA BUS MOVE FIELDSU
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APPENDIX BBENCHMARK PROGRAMS-
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B.1 INTRODUCTIONTable 8-1 provides
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page 132,66,0,6opt rc.*************
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;This program originally available
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page 132,66,0,6opt rc...._..__.....
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page 132,60,1,1;newlms2n.asm; New I
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,; Main program to call the rfft-56
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jle -'oopmove xO,rOmove y1,amove x:
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FirstGrouplnPassdo nO,FirstGrouplnP
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; Real input data are split into tw
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zero (bit 2) .................... 5
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-M- OnCE Commands .................
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Saturation Arithmetic .............
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DSP56K FAMILY INTRODUCTION_DSP56K C