section 7 - Index of

DO Start Hardware Loop DOmented by two. Instruction fetches now continue at the address of the instruction followingthe last instruction in the DO loop. Note that LF is the only bit in the status register(SR) that is restored after a hardware DO loop has been exited.Note: The loop flag (LF) is cleared by a hardware reset.-Restrictions: The "end-of-Ioop" comparison previously described actually occurs atinstruction fetch time. That is, LA is being compared with PC when the instruction at LA-2 is being executed. Therefore, instructions which access the program controller registersand/or change program flow cannot be used in locations LA-2, LA-1, or LA.Proper DO loop operation is not guaranteed if an instruction starting at address LA-2,L~-1, or LA specifies one of the program controller registers SR, SP, SSL, LA, LC, or(implicitly) PC as a destination register. Similarly, the SSH program controller registermay not be specified as a source or destination register in an instruction starting ataddress LA-2, LA-1, or LA. Additionally, the SSH register cannot be specified as asource register in the DO instruction itself and LA cannot be used as a target for jumpsto subroutine (Le., JSR, JScc, JSSET, or JSCLR to LA). A DO instruction cannot berepeated using the REP instruction.The following instructions cannot begin at the indicated position(s) near the end of a DOloop:At LA-2, LA-1, and LAAt LA-1DOMOVEC from SSHMOVEM from SSHMOVEP from SSHMOVEC to LA, LC, SR, SP, SSH, or SSLMOVEM to LA, LC, SR, SP, SSH, or SSLMOVEP to LA, LC, SR, SP, SSH, or SSLANDI MRORIMRTwo-word instructions which read LC, SP, or SSLSingle-word instructions (except REP) which read LC,SP, or SSL, JCLR, JSET, two-word JMP, two-word Jcc