section 7 - Index of

Case 2: One of the more common sequences where pipeline effects are apparent is asfollows:;Move a number into register Rn (n=0-7).MOVE #xx,RnMOVE X:(Rn),A;Use the new contents of Rn to address memory.In this case, before the first MOVE instruction has written Rn during its execution cycle,the second MOVE has accessed the old Rn, using the old contents of Rn. This isbecause the address for indirect moves is formed during the decode cycle. This overlappinginstruction execution in the pipeline causes the pipeline effect. One instruction cycleshould be allowed after an address register has been written by a MOVE instructionbefore the new contents are available for use as an address register by another MOVEinstruction. The proper instruction sequence is as follows:MOVEXO,RnNOPMOVE X:(Rn),A;Move a number into register Rn.;Execute any instruction or instruction;sequence not using Rn.Use the new contents of Rn.Case 3: A situation related to Case 2 can be seen in the boot ROM code shown in AP­PENDIX A of the DSP56001 Technical Data Sheet. At the end of the bootstrap operation,the operation mode register (OMR) is changed to mode #2, and then the program that wasloaded is executed. This process is accomplished in the last three instructions:--BOOTEND MOVEC #2,OMR ;Set the operating mode to 2;(and trigger an exit from;bootstrap mode).ANDI #$O,CCR ;Clear SR as if RESET and;introduce delay needed for;Op. Mode change.JMP