section 7 - Index of

OR Logical Inclusive OR OROperation:Assembler Syntax:8+0[47:24] -+ 0[47:24] (parallel move) OR 8,0 (parallel move)where + denotes the logical inclusive OR operatorDescription: Logically inclusive OR the source operand 8 with bits 47-24 of the destinationoperand 0 and store the result in bits 47-24 of the destination accumulator. Thisinstruction is a 24-bit operation. The remaining bits of the destination operand 0 are notaffected.Example:OR Y1,B1 BA,L:$1234 ;save A1 ,B1, OR Y1 with BBefore ExecutionAfter ExecutionY11 ~ _________ $_FF_O_OO_o __ ~ Y1 ~I ________._$_FF_O_OO_o __ ~BI ~ ____ $0_O:_12_34_56_:7_8_9A_B_C __ ~B~I ____ $0_O:_FF_3_45_6:7_8_9A_B_C __ ~Explanation of Example: Prior to execution, the 24-bit Y1 register contains the value$FFOOOO, and the 56-bit B accumulator contains the value $00:123456:789ABC. The ORY1 ,B instruction logically ORs the 24-bit value in the Y1 register with bits 47-24 of the Baccumulator (B1) and stores the result in the B accumulator with bits 55-48 and 23-0unchanged.Condition Codes:I LF I OM I T I·· I 81 I 80 I 1115 14 13 12 11 10 9 8 7 6 5 4 3 2 0I 10 I s I LIE I u I N I z I v I :. I.~ MR •. ~ eeR _.8 - Computed according to the definition in A.5 CONDITION CODE COMPUTATIONL - 8et if data limiting has occurred during parallel moveN - Set if bit 47 of A or B result is setZ - Set If bits 47-24 of A or B result are zeroV - Always cleared