section 7 - Index of

8TSTBit Test8TSTInstruction Format:BTST #n,DOpcode:23 16 1510 0 0 0 1 0 18 7 oo I 0 1 1 b b b b blInstruction Fields:#n=bit number=bbbbb,D=destination register=DDDDDD,xxxx=16-bit Absolute Address in extension wordDestination RegisterDDDDDD4 registers in Data ALU o 0 0 1 D D8 accumulators in Data ALU o 0 1 D D D8 address registers in AGU o 1 0 T T T8 address offset registers ilJ AGU o 1 1 N N N8 address modifier registers in AGU 0 0 F F F8 program controller registers 1 1 G G GBit Number bbbbb00000•10111See Section A.1 0 and Table A-18 for specific register encodings.Notes: If A or B is specified as the destination operand, the following sequence of eventstakes place:1. The S bit is computed according to its definition (See Section A.S)2. The accumulator value is scaled according to the scaling mode bits SOand S1 in the status register (SR).3. If the accumulator extension is in use, the output of the shifter is limitedto the maximum positive or negative saturation constant, and the L bit isset.4. The bit test is performed on the resulting 24-bit value and the C bit is setif the bit tested is~ set. The original contents of A or B are not changed.Timing: 4+mvb oscillator clock cyclesMemory: 1 +ea program words