section 7 - Index of

Section A.10.4 gives the encoding for the data ALU portion of those instructions whichallow parallel data moves. These a-bit partial instruction codes may be combined withthe 16-bit parallel move opcodes listed in Section A.10.1 to form a complete 24-bitinstruction word.A.10.1 Partial Encodings for Use in Instruction EncodingTable A-15 Single-Bit Register EncodingsCode d* e f Where:0 A XO YO d = 2 Accumulators in Data ALU1 B X1 Y1 e = 2 Registers in Data ALU• For class II encodings for R:Y and X:R, see Table A-16f = 2 Registers in Data ALUTable A-16 Single-Bit Special Register Encodingsd X:R Class II Opcode R:Y Class II Opcode0 A ~ X: XO ~ A YO ~ AA ~ Y:1 B ~ X: XO ~ B YO ~ B B ~ Y:Table A-17 Double-Bit Register EncodingsCode DD ee00 XO XO01 X1 X110 YO A11 Y1 BffYOY1ABWhere: DD = 4 registers in data ALUee = 4 XDS registers in data ALUff = 4 YDS registers in data ALU-