section 7 - Index of

The DSP56K family is not designed for a particular application butis designed to executecommonly used DSP benchmarks in a minimum time for a single-multiplier architecture.For example, a cascaded, 2nd-order, four-coefficient infinite impulse response (IIR) biquadsection has four multiplies for each section. For that algorithm, the theoreticalminimum number of operations for a Single-multiplier architecture is four per section. Table1-1 shows a list of benchmarks with the number of instruction cycles a DSP56K chipuses compared to the number of multiplies the algorithm requires.Table 1-1 Benchmark Summary in Instruction CyclesBenchmarkDSP56000/DSP56001Number of CyclesNumber ofAlgorithmMultipliesReal Multiply 3 1N Real Multiplies 2N NReal Update 4 1N Real Updates 2N NN Term Real Convolution (FIR) N NN Term Real * Complex Convolution 2N NComplex Multiply 6 4N Complex Multiplies 4N NComplex Update 7 4N Complex Updates 4N 4NN Term Complex Convolution (FIR) 4N 4NNth -Order Power Series 2N 2N2 nd - Order Real Biquad Filter 7 4N Cascaded 2 nd - Order Biquads 4N 4NN Radix Two FFT Butterflies 6N 4NThese benchmarks and others are used independently or in combination to implementfunctions whose characteristics are controlled by the coefficients of the benchmarks beingexecuted. Useful functions using these and other benchmarks include the following: