section 7 - Index of

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7.3.7 Interrupt Instruction ExecutionInterrupt instruction execution is considered "fast" if neither of the instructions of theinterrupt service routine causes a change of flow. A JSR within a fast interrupt routineforms a long interrupt, which is terminated with an RTI instruction to restore the PC andSR from the stack and return to normal program execution. Reset is a special exception,which will normally contain only a JMP instruction at the exception start address. At theprogrammer's option, almost any instruction can be used in the fast interrupt routine. Therestricted instructions include SWI, STOP, and WAIT. Figure 7-8 and Figure 7-10 showthe fast and the long interrupt service routines. The fast interrupt executes only twoinstructions and then automatically resumes execution of the main program; whereas,the long interrupt must be told to return to the main program by executing an RTI instruction.Figure 7-8 illustrates the effect of a fast interrupt routine in the stream of instructionfetches.-Figure 7-9 shows the sequence of instruction decodes between two fast interrupts. Fourdecodes occur between the two interrupt decodes (two after the first interrupt and twopreceding the second interrupt). The requirement for these four decodes establishes themaximum rate at which the DSP56K will respond to interrupts - namely, one interruptevery six instructions (six instruction cycles if all six instructions are one instruction cycleeach). Since some instructions take more than one instruction cycle, the minimum numberof instructions between two interrupts may be more than six instruction cycles.The execution of a fast interrupt routine always conforms to the following rules:1. A JSR to the starting address of the interrupt service routine is notiocated atone of the two interrupt vector addresses.2. The processor status is not saved.3. The fast interrupt routine may (but should not) modify the status of the normalinstruction stream.4. The fast interrupt routine may contain any single two-word instruction or anytwo one-word instructions except SWI, STOP, and WAIT.5. The PC, which contains the address of the next instruction to be executed innormal processing remains unchanged during a fast interrupt routine.
MAINPROGRAMMEMORYIINTERRUPT SYNCHRONIZEDAND RECOGNIZEDAS PENDING_n1ADDITIONAL INTERRUPTSn2DISABLED DURING I-------~FAST INTERRUPT 1--__ n_3 __---In4INTERRUPTS_ 1--------1RE-ENABLEDii = INTERRUPT INSTRUCTIONn = NORMAL INSTRUCTION(a) Instruction Fetches from Memory-INTERRUPT SYNCHRONIZED ANDRECOGNIZED AS PENDINGINTERRUPTS RE-ENABlEDINTERRUPT CONTROL CYCLE 1iINTERRUPT CONTROL CYCLE 2iFETCHn1n2 ii1 ii2 n3n4DECODEn1 n2 ii1 ii2n3n4EXECUTEn1 n2 ii1ii2n3n4iinINSTRUCTION CYCLE COUNTINTERRUPTINTERRUPT INSTRUCTION WORD= NORMAL INSTRUCTION WORD12 3 4 567 8(b) Program Controller PipelineFigure 7-8 Fast Interrupt Service Routine
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DSP56K FAMILY INTRODUCTIONDSP56K CE
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Motorola reserves the right to make
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Table of Contents (Continued)Paragr
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ParagraphNumberTable of Contents (C
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FigureNumberList of Figures (Contin
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List of Tables (Continued)TablePage
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1.1 INTRODUCTIONThe DSP56K family i
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Fewer componentsStable, determinist
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Digital FilteringFinite Impulse Res
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architecture matches the shape of t
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• DSP56001 Compatibility - All me
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SECTION 2DSP56K CENTRAL ARCHITECTUR
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--I«a:w:ca.ffi~a. a.24-Bit 56KModu
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-rectly addressable registers: the
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3.1 DATA ARITHMETIC LOGIC UNITThis
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3.2.1 Data ALU Input Registers (X1,
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"""""" 24 BITS;:~:>~~::~~~:~:~:~:::
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3.2.4 Accumulator ShifterThe accumu
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Table 3-1 Limited Data ValuesDestin
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_--- N BITS ---_TWOS COMPLEMENT INT
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CASE I: IF AO < $800000 (1/2), THEN
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one instruction cycle. The ANDI ins
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3.5 DATA ALU PROGRAMMING MODELThe D
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4.1 ADDRESS GENERATION UNIT AND ADD
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!---LOWADDRESS ALU -----I~.j.I.....
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•••••••• _ ........
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4.4.1 Address Register Indirect Mod
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EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
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EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
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EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
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Table 4-2 Address Modifier SummaryM
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ADDRESS -f-_POINTERUPPER BOUNDARYiM
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EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
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oundary gives a 16-bit binary numbe
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4.4.2.4 Address-Modifier-Type Encod
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SECTION 5PROGRAM CONTROL UNIT-
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X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
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interruptible since they are fetche
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PROGRAM CONTROL UNIT-23 1615 023 16
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The GGR is a special purpose contro
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If S 1 =0 and SO=O (no scaling)then
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-23 876543210I * 1* JSO I * I Mel y
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5.4.5.1 Stack Pointer (Bits 0-3)The
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-DATA ARITHMETIC LOGIC UNITINPUT RE
Page 101 and 102: 6.1 INSTRUCTION SET INTRODUCTIONThe
Page 103 and 104: shown in Figure 6-2. Most instructi
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Page 107 and 108: The MR and CCR may be accessed indi
Page 109 and 110: 6.3.4 Operand ReferencesThe DSP sep
Page 111 and 112: Some address register indirect mode
Page 113 and 114: EXAMPLE A: IMMEDIATE INTO 24-BIT RE
Page 115 and 116: EXAMPLE A: IMMEDIATE SHORT INTO AO,
Page 117 and 118: EXAMPLE A: MOVE P: $3200,XOBEFORE E
Page 119 and 120: Table 6-1 Addressing Modes SummaryA
Page 121 and 122: 6.4.2 LogicallnstructlonsThe logica
Page 123 and 124: START OF LOOP1)SP+ 1 • SP; LA. SS
Page 125 and 126: OPCODE/OPERANDSPARALLEL MOVE EXAMPL
Page 127: SECTION 7PROCESSING STATES-
Page 130 and 131: Each instruction requires a minimum
Page 132 and 133: second instruction of the downloade
Page 134 and 135: The DO instruction is another instr
Page 136 and 137: SP and SSH/SSL register manipulatio
Page 138 and 139: 7.3.1 Interrupt TypesThe DSP56K rel
Page 140 and 141: Table 7-2 Status Register Interrupt
Page 142 and 143: 7.3.3 Interrupt SourcesInterrupts c
Page 144 and 145: interrupts makes it very useful for
Page 146 and 147: MAINPROGRAMFETCHESLONG INTERRUPTSER
Page 148 and 149: 7.3.3.3 Other Interrupt SourcesOthe
Page 150 and 151: 7.3.4 Interrupt ArbitrationInterrup
Page 154 and 155: MAINPROGRAMMEMORYINTERRUPT SYNCHRON
Page 156 and 157: MAINPROGRAMFETCHESINTERRUPTSYNCHRON
Page 158 and 159: MAINPROGRAMFAST INTERRUPTVECTORLONG
Page 160 and 161: MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
Page 162 and 163: 7.5 WAIT PROCESSING STATEThe WAIT i
Page 164 and 165: The stop processing state halts all
Page 166 and 167: the first instruction fetch). If th
Page 168: RESET -----------------------------
Page 172 and 173: 16 - BIT INTERNALADDRESS BUSESX ADD
Page 174 and 175: 8.2.2.1 Address (AO-A15)These three
Page 177: SECTION 9PLL CLOCK OSCILLATOR-
Page 180 and 181: X MEMORYRAM/ROMEXPANSION24-Bit56KMo
Page 182 and 183: 23 22 21 20 19 18 17 16 15 14 13 12
Page 184 and 185: cleared. To enable rapid recovery w
Page 186 and 187: -CLVCCVCC for the CKOUT output. The
Page 188 and 189: 4. For all input frequencies which
Page 190 and 191: While the PLL is regaining lock, th
Page 193 and 194: 10.1 ON-CHIP EMULATION INTRODUCTION
Page 195 and 196: 10.2.2 Debug Serial Clock/Chip Stat
Page 197 and 198: 76543210I R/W I GO I EX I RS41 RS31
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Page 201 and 202: 10.3.4.4 Software Debug Occurrence
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10.4.4 Memory High Address Comparat
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10.6.1 External Debug Request Durin
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PABCIRCULARBUFFERPOINTERDSCKDSOFigu
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are serially available to the exter
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k. ACKI. ClKm. Send command READ FI
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19. ACK20. Send command READ GDB RE
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10.11.6.1 Case 1: Return To The Pre
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SECTION 11ADDITIONAL SUPPORTDr. BuB
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The following is a partial list of
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• In-line assembler language code
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I Document 10 I Version Synopsis I
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I Document ID I Version Synopsis I
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11.5 MOTOROLA DSP NEWSThe Motorola
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DIGITAL SIGNAL PROCESSINGAlan V. Op
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C Programming Language:Controls:. C
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Image Processing:DIGITAL IMAGE PROC
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LINEAR PREDICTION OF SPEECHJ. D. Ma
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A.1 APPENDIX A INTRODUCTIONThis app
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XnYnTable A-1 Instruction Descripti
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Table A-1 Instruction Description N
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Table A-1 Instruction Description N
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Table A-2 DSP56K Addressing ModesAd
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The address register indirect addre
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A.SCONDITION CODE COMPUTATION15 14
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S1 SO Scaling Mode Signed Integer P
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Table A-5 Condition Code Computatio
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A.7 INSTRUCTION DESCRIPTIONSThe fol
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ABSAbsolute ValueABSInstruction For
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ADC Add Long with Carry ADCresult.
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ADD Add ADDCondition Codes:15 14 13
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ADDL Shift Left and Add Accumulator
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ADDR Shift Right and Add Accumulato
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ANDLogical ANDANDInstruction Format
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ANDIAND Immediate with Control Regi
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ASL Arithmetic Shift Accumulator Le
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ASR Arithmetic Shift Accumulator Ri
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BCHG Bit Test and Change BCHGExplan
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BCHGBit Test and ChangeBCHGInstruct
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BCHGBit Test and ChangeBCHGInstruct
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BCHG Bit Test and Change BCHGNotes:
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BCLR Bit Test and Clear BCLRExplana
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BClRBit Test and ClearBClRInstructi
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BClRBit Test and ClearBClRInstructi
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BClR Bit Test and Clear BClRNotes:
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BSET Bit Test and Set BSETExplanati
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BSETBit Test and SetBSETInstruction
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BSETBit Test and SetBSETInstruction
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BSET Bit Test and Set BSETNotes: If
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BTSTBit TestBTSTCondition Codes:115
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8TSTBit Test8TSTInstruction Format:
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8TSTBit Test8TSTInstruction Format:
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CLRClear AccumulatorCLRInstruction
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CMP Compare CMPCondition Codes:15 1
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CMPM Compare Magnitude CMPMConditio
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DEBUGEnter Debug ModeDEBUGOpcode:23
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DEBUGcc Enter Debug Mode Conditiona
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DEC Decrement by One DECInstruction
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DIV Divide Interation DIVThe DIV in
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DIV Divide Interation DIVNote that
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DIVInstruction Format:DIV S,DDivide
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DO Start Hardware Loop DOexecuted 6
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DOStart Hardware LoopDOAt LAOther R
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DOStart Hardware LoopDOInstruction
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DOStart Hardware LoopDOInstruction
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DO Start Hardware Loop DONotes: If
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ENDDO End Current DO Loop ENDDOExpl
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EOR Logical Exclusive OR EORInstruc
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ILLEGALIllegal Instruction Interrup
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INC Increment by One INCInstruction
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Jcc Jump Conditionally JccRestricti
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JccJump ConditionallyJccEffectiveAd
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JCLR Jump If Bit Clear JCLRRestrict
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JCLRJump If Bit ClearJCLRInstructio
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JCLR Jump If Bit Clear JCLRInstruct
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JMPJumpJMPInstruction Fields:xxx=12
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JSccJump to Subroutine Conditionall
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JScc Jump to Subroutine Conditional
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JSCLR Jump to Subroutine if Bit Cle
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JSCLRJump to Subroutine If Bit Clea
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JSCLRJump to Subroutine If Bit Clea
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JSCLR Jump to Subroutine If Bit Cle
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JSET Jump if Bit Set JSETRestrictio
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JSETJump if Bit SetJSETInstruction
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JSET Jump If Bit Set JSETInstructio
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JSR Jump to Subroutine JSRInstructi
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JSSET Jump to Subroutine if Bit Set
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JSSETJump to Subroutine if Bit SetJ
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JSSET Jump to Subroutine if Bit Set
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LSL Logical Shift Left LSLCondition
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LSR Logical Shift Right LSRConditio
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LUALoad Updated AddressLUACondition
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MAC Signed Multiply-Accumulate MACC
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MACSigned Multiply-AccumulateMACTim
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MACR Signed Multiply-Accumulate and
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MACR Signed MUltiply-Accumulate and
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MOVE Move Data MOVEExplanation of E
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MOVE Move Data MOVEWhen a 56-bit ac
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No Parallel Data MoveInstruction Fo
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I Immediate Short Data Move IExampl
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I Immediate Short Data Move IDDD d
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R Register to Register Data Move RE
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R Register to Register Data Move RI
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uAddress Register UpdateuInstructio
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X: X Memory Data Move X:Note:Due to
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X: X Memory Data Move X:S D DS,D d
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X: X Memory Data Move X:S D DS,D d
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X:R X Memory and Register Data Move
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Y: Y Memory Data Move Y:Note: This
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Y: Y Memory Data Move Y:S D DS,D d
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Y: Y Memory Data Move Y:S D DS,D d
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R:V Register and V Memory Data Move
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R:V Register and Y Memory Data Move
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R:V Register and Y Memory Data Move
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L: Long Memory Data Move L:Example:
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L: Long Memory Data Move L:Instruct
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X: Y: xv Memory Data Move X: Y:Exam
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X: Y: xv Memory Data Move X: Y:S1 D
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MOVEC Move Control Register MOVECst
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MOVEC Move Control Register MOVECCo
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MOVECMove Control RegisterMOVECInst
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MOVEC Move Control Register MOVECTi
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MOVEM Move Program Memory MOVEMoper
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MOVEM Move Program Memory MOVEMInst
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MOVEMMove Program MemoryMOVEMInstru
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MOVEP Move Peripheral Data MOVEPist
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MOVEP Move Peripheral Data MOVEPCon
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MOVEP Move Peripheral Data MOVEPIns
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MOVEP Move Peripheral Data MOVEPIns
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MPY Signed Multiply MPYExplanation
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MPY Signed Multiply MPYInstruction
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MPYR Signed Multiply and Round MPYR
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MPYR Signed Multiply and Round MPYR
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NEGNegate AccumulatorNEGInstruction
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NOPNo OperationNOPInstruction Forma
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NORM Normalize Accumulator Iteratio
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NOTLogical ComplementNOTInstruction
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ORLogical Inclusive ORORInstruction
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ORI OR Immediate with Control Regis
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REP Repeat Next Instruction REPRest
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REPRepeat Next InstructionREPInstru
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REPRepeat Next InstructionREPInstru
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REP Repeat Next Instruction REPNote
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RESETReset On-Chip Peripheral Devic
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RND Round Accumulator RNDConvergent
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RNDRound AccumulatorRNDInstruction
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ROL Rotate Left ROLCondition Codes:
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ROR Rotate Right RORCondition Codes
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RTIReturn from InterruptRTIConditio
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RTSReturn from SubroutineRTSInstruc
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sec Subtract Long with Carry secExp
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secSubtract Long with CarrysecInstr
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STOPStop Instruction ProcessingSTOP
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SUB Subtract SUBCondition Codes:S -
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SUBL Shift Left and Subtract Accumu
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SUBR Shift Right and Subtract Accum
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SWISoftware InterruptSWICondition C
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Tee Transfer Conditionally Teetion
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Tee Transfer Conditionally TeeInstr
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TFR Transfer Data ALU Register TFRC
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TSTTest AccumulatorTSTInstruction F
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WAIT Wait for Interrupt WAITConditi
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including the number of words per i
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5. Compute final results.Thus, base
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JLC (R2+N2)will requireand will exe
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Table A-6 Instruction Timing Summar
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Note that the "ap" term in Table A-
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Table A-14 Memory Access Timing Sum
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Other RestrictionsDO SSH,xxxxJSR to
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Immediately before MOVEC from SSH o
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A.9.S REP RestrictionsThe REP instr
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Table A-18 Triple-Bit Register Enco
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Table A-24 Program Control Unit Reg
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R: Register to Register Parallel Da
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JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
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JSSET#n,S,xxxx23 16 15 87 000001011
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BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
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MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
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LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
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ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
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Table A-28 Operation Code QQQ Decod
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Table A-30 Special Case #10 P E R C
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NEGD23 87 43 0DATA BUS MOVE FIELDLS
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ADDRS,D23 87 43 oDATA BUS MOVE FIEL
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lEI
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Table 8-1 27-MHz Benchmark Results
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.*._---*-----*-------**-------....
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;Latest Revision - September 30, 19
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All coefficients are divided by 2:w
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Real input FFT based on Glenn Bergl
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countountcountcountorg y:coefset 0d
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; Real-Valued FFT for MOTOROLA DSP5
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; first group in the last passmove
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A Accumulator ....... ' ...........
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-H- fast ..........................
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PGND ..............................
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DSP56K FAMILY INTRODUCTIONDSP56K CE
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