section 7 - Index of

Table 7-3 Interrupt Priority Level BitsTable 7-4 External InterruptxxL1 xxLO Enabled IPL IxL2 Trigger Mode0 0 No - 0 Level0 1 Yes 0 1 Negative Edge1 0 Yes 11 1 Yes 27.3.2.2 Exception Priorities Within an IPLIf more than one interrupt is pending when an instruction is executed, the processor willservice the interrupt with the highest priority level first. When multiple interrupt requestswith the same IPL are pending, a second fixed-priority structure within that IPL determineswhich interrupt the processor will service. The fixed priority of interrupts within anIPL and the interrupt enable bits for all interrupts are shown in Table 7-5.Table 7-5 Central Processor Interrupt Priorities Within an IPLPriority Exception Enabled By Bit No.X DataMemoryAddressLevel 3 (Nonmaskable)Highest Hardware RESET - - -III - - -NMI - - -Stack Error - - -Trace - - -Lowest SWI - - -Levels 0, 1,2 (Maskable)Higher IROA (External Interrupt) IROA Mode Bits o and 1 $FFFFLower IROB (External Interrupt) IROB Mode Bits 3 and 4 $FFFF