section 7 - Index of

A.SCONDITION CODE COMPUTATION15 14 13 12 11 10 9 8 7 6 4 3 2 oI'F 10M I T I ** I 51 I SO I 11 I 10 I 5 I l I E I u N I z.. MA .. oC eeAThe condition code register (CCR) portion of the status register (SR) consists of eightdefined bits:S -L -Scaling BitLimit BitN -Z -Negative BitZero BitE - Extension Bit V - Overflow BitU - Unnormalized Bit C - Carry BitThe E, U, N, Z, V, and C bits are true condition code bits that reflect the condition of theresult of a data ALU operation. These condition code bits are not latched and are notaffected by address ALU calculations or by data transfers over the X, Y, or globaldata buses. The L bit is a latching overflow bit which indicates that an overflow hasoccurred in the data ALU or that data limiting has occurred when moving the contents ofthe A and/or B accumulators. The S bit is a latching bit used in block floating pOint operationsto indicate the need to scale the number in A or B. See SECTION 5 - PROGRAMCONTROL UNIT for information on the MR portion of the status register.The standard definition of the condition code bits follows. Exceptions to these standarddefinitions are given in the notes which follow Table A-5.