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WITHOUT L1MITING*WITH L1MITING*~ 0 ~ 010 .. ,01~0, .......... 00100 ............ 001 A=+1.0 10 ... 0 I~O, .......... 001 00 ............ 001 A=+1.07 0 23 rl 0 23 0V MOVE A1, XO11.. 0 ........... 0 0 1 xo = -1.0l7 0 23 rl 0 23 0V MOVE A, XOI~ 1 ........... 111 XO=+0.9999999-.23 0 IERRORI = 2.0 23 0 IERRORI = .0000001* Limiting automatically occurs when the 56 - bit operands A or B (not A2, A1, AO, B2, B1, or BO) are read. The contents<strong>of</strong> A or B are NOT changed.Figure 3-5 Saturation ArithmeticFor example, if the source operand were 01.100 (+ 1.5 decimal) and the destination registerwere only four bits, the destination register would contain 1.100 (- 1.5 decimal) afterthe transfer, assuming signed fractional arithmetic. This is clearly in error as overflow hasoccurred. To minimize the error 'due to overflow, it is preferable to write the maximum("limited") value the destination can assume. In the example, the limited value would be0.111 (+ 0.875 decimal), which is clearly closer to + 1.5 than - 1.5 and therefore introducesless error.Figure 3-5 shows the effects <strong>of</strong> saturation arithmetic on a move from register A 1 to registerXO. The instruction "MOVE A1 ,XO" causes a move without limiting, and the instruction"MOVE A,XO" causes a move <strong>of</strong> the same 24 bits with limiting. The error without limitingis 2.0; whereas, it is 0.0000001 with limiting. Table 3-1 shows a more complete set <strong>of</strong> limitingsituations.3.2.5.2 ScalingThe data shifters can shift data one bit to the left or one bit to the right, or pass the dataunshifted. Each data shifter has a 24-bit output with overflow indication and is controlledby the scaling mode bits in the status register. These shifters permit dynamic scaling <strong>of</strong>fixed-point data without modifying the program code. For example, this permits block floating-pointalgorithms such as fast Fourier transforms to be implemented in a regularfashion.3.3 DATA REPRESENTATION AND ROUNDINGThe DSP56K uses a fractional data representation for all Data ALU operations. Figure 3-7 shows the bit weighting <strong>of</strong> words, long words, and accumulator operands for this representation.The decimal pOints are all aligned and are left justified.

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