section 7 - Index of

Table A-7 Parallel Data Move TimingParallel Move Operation+mvWords+mvCyclesNo Parallel Data Move 0 0I Immediate Short Data 0 0R Register to Register 0 0U Address Register Update 0 0CommentsX: X Memory Move ea ea+ ax See Note 1X:R X Memory and Register ea ea+ ax See Note 1Y: Y Memory Move ea ) ea+ ay See Note 1R:Y Y Memory and Register ea ea+ ay See Note 1L: Long Memory Move ea ea + axyX:Y: XV Memory Move 0 ea+ axyLMS(X) LMS X Memory Moves 0 ea+ ax See Notes 1 ,2LMSM LMS Y Memory Moves 0 ea+ ay See Notes 1 ,2Note 1: The ax or ay term does not apply to MOVE IMMEDIATE DATA.Note 2: The ea term does not apply to ABSOLUTE ADDRESS and IMMEDIATE DATA.Table A-a MOVEC Timing Summary (see Note 2)MOVEC Operation+mvcCyclesImmediate Short 4 Register 0Register +-+ Register 0CommentsX Memory+-+ Register ea+ax See Note 1Y MemoryB Register ea + ay See Note 1P Memory+-+ Register4+ ea+ apNote 1: The ax or ay term does not apply to MOVE IMMEDIATE DATA.Note 2: If assumption 4 is not applicable, then to each one-word instruction timing, a "+ ap" term shouldbe added, and to each two-word instruction, a "+ (2 * ap)" term should be added to account forthe program memory wait states spent to fetch an instruction word to fill the pipeline.Table A-9 MOVEP Timing Summary (see Note 2)-MOVEP Operation+mvpCyclesCommentsRegister+-+ Peripheral aio See Note 3Register+-+ Peripheral 2+aio See Note 4X Memory-0- Peripheral 2 + ea + ax + aio See Note 1Y Memory+-+ Peripheral 2 + ea + ay + aio See Note 1P Memory+-+ Peripheral4 + ea + ap + aioNote 1: The" 2+ax" or "2+ay" terms do not apply to MOVE IMMEDIATE DATA.Note 2: If assump:ion 4 is not applicable, then to each one-word instruction timing,a "+ ap" term should beadded, and to each two-word instruction, a "+ (2 * ap)" term should be added to account for theprogram memory wait states spent to fetch an instruction word to fill the pipeline.Note 3: "Register" refers to DATA_ALU registerNote 4: "Register" refers to non DATA_ALU register