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11.1 USER SUPPORTUser support from the conception of a design through completion is available fromMotorola and third-party companies as shown in the following list:DesignPrototypingDesignVerificationMotorolaData SheetsApplication NotesApplication BulletinsSoftware ExamplesAssemblerLinkerC CompilerSimulatorApplication DevelopmentSystem (ADS)In-Circuit EmulatorCable for ADSApplication DevelopmentSystem (ADS)In-Circuit EmulatorSimulatorThird PartyData Acquisition PackagesFilter Design PackagesOperating System SoftwareSimulatorLogic Analyzer withDSP56000/DSP56001 ROM PackagesIn-Circuit EmulatorsData Acquisition CardsDSP Development System CardsOperating System SoftwareDebug SoftwareData Acquisition PackagesLogic Analyzer withDSP56000/DSP56001 ROM PackagesData Acquisition CardsDSP Development System Cards ..Application-Specific Development ToolsDebug Software-
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DSP56K FAMILY INTRODUCTIONDSP56K CE
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Motorola reserves the right to make
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Table of Contents (Continued)Paragr
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ParagraphNumberTable of Contents (C
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FigureNumberList of Figures (Contin
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List of Tables (Continued)TablePage
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1.1 INTRODUCTIONThe DSP56K family i
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Fewer componentsStable, determinist
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Digital FilteringFinite Impulse Res
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architecture matches the shape of t
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• DSP56001 Compatibility - All me
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SECTION 2DSP56K CENTRAL ARCHITECTUR
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--I«a:w:ca.ffi~a. a.24-Bit 56KModu
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-rectly addressable registers: the
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3.1 DATA ARITHMETIC LOGIC UNITThis
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3.2.1 Data ALU Input Registers (X1,
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"""""" 24 BITS;:~:>~~::~~~:~:~:~:::
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3.2.4 Accumulator ShifterThe accumu
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Table 3-1 Limited Data ValuesDestin
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_--- N BITS ---_TWOS COMPLEMENT INT
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CASE I: IF AO < $800000 (1/2), THEN
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one instruction cycle. The ANDI ins
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3.5 DATA ALU PROGRAMMING MODELThe D
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4.1 ADDRESS GENERATION UNIT AND ADD
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!---LOWADDRESS ALU -----I~.j.I.....
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•••••••• _ ........
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4.4.1 Address Register Indirect Mod
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EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
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EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
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EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
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Table 4-2 Address Modifier SummaryM
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ADDRESS -f-_POINTERUPPER BOUNDARYiM
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EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
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oundary gives a 16-bit binary numbe
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4.4.2.4 Address-Modifier-Type Encod
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SECTION 5PROGRAM CONTROL UNIT-
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X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
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interruptible since they are fetche
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PROGRAM CONTROL UNIT-23 1615 023 16
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The GGR is a special purpose contro
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If S 1 =0 and SO=O (no scaling)then
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-23 876543210I * 1* JSO I * I Mel y
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5.4.5.1 Stack Pointer (Bits 0-3)The
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-DATA ARITHMETIC LOGIC UNITINPUT RE
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6.1 INSTRUCTION SET INTRODUCTIONThe
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shown in Figure 6-2. Most instructi
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23 87 0L...-I ___-'-I_---'I BUS~ LS
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The MR and CCR may be accessed indi
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6.3.4 Operand ReferencesThe DSP sep
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Some address register indirect mode
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EXAMPLE A: IMMEDIATE INTO 24-BIT RE
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EXAMPLE A: IMMEDIATE SHORT INTO AO,
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EXAMPLE A: MOVE P: $3200,XOBEFORE E
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Table 6-1 Addressing Modes SummaryA
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6.4.2 LogicallnstructlonsThe logica
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START OF LOOP1)SP+ 1 • SP; LA. SS
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OPCODE/OPERANDSPARALLEL MOVE EXAMPL
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SECTION 7PROCESSING STATES-
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Each instruction requires a minimum
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second instruction of the downloade
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The DO instruction is another instr
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SP and SSH/SSL register manipulatio
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7.3.1 Interrupt TypesThe DSP56K rel
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Table 7-2 Status Register Interrupt
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7.3.3 Interrupt SourcesInterrupts c
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interrupts makes it very useful for
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MAINPROGRAMFETCHESLONG INTERRUPTSER
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7.3.3.3 Other Interrupt SourcesOthe
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7.3.4 Interrupt ArbitrationInterrup
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7.3.7 Interrupt Instruction Executi
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MAINPROGRAMMEMORYINTERRUPT SYNCHRON
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MAINPROGRAMFETCHESINTERRUPTSYNCHRON
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MAINPROGRAMFAST INTERRUPTVECTORLONG
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MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
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7.5 WAIT PROCESSING STATEThe WAIT i
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The stop processing state halts all
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the first instruction fetch). If th
Page 168: RESET -----------------------------
Page 172 and 173: 16 - BIT INTERNALADDRESS BUSESX ADD
Page 174 and 175: 8.2.2.1 Address (AO-A15)These three
Page 177: SECTION 9PLL CLOCK OSCILLATOR-
Page 180 and 181: X MEMORYRAM/ROMEXPANSION24-Bit56KMo
Page 182 and 183: 23 22 21 20 19 18 17 16 15 14 13 12
Page 184 and 185: cleared. To enable rapid recovery w
Page 186 and 187: -CLVCCVCC for the CKOUT output. The
Page 188 and 189: 4. For all input frequencies which
Page 190 and 191: While the PLL is regaining lock, th
Page 193 and 194: 10.1 ON-CHIP EMULATION INTRODUCTION
Page 195 and 196: 10.2.2 Debug Serial Clock/Chip Stat
Page 197 and 198: 76543210I R/W I GO I EX I RS41 RS31
Page 199 and 200: shifted in (so a new command is ava
Page 201 and 202: 10.3.4.4 Software Debug Occurrence
Page 203 and 204: 10.4.4 Memory High Address Comparat
Page 205 and 206: 10.6.1 External Debug Request Durin
Page 207 and 208: PABCIRCULARBUFFERPOINTERDSCKDSOFigu
Page 209 and 210: are serially available to the exter
Page 211 and 212: k. ACKI. ClKm. Send command READ FI
Page 213 and 214: 19. ACK20. Send command READ GDB RE
Page 215 and 216: 10.11.6.1 Case 1: Return To The Pre
Page 217: SECTION 11ADDITIONAL SUPPORTDr. BuB
Page 221 and 222: the DSP56K family of processors•
Page 223 and 224: 11.3.3 Support Integrated Circuits:
Page 225 and 226: I Document ID I Version Synopsis I
Page 233 and 234: 11.12 TRAINING COURSES - (602) 897-
Page 235 and 236: ADAPTIVE SIGNAL PROCESSINGB. Widrow
Page 237 and 238: Graphics:CGM AND CGID. B. Arnold an
Page 239 and 240: NUMERICAL RECIPES IN C - THE ART OF
Page 241: APPENDIX AINSTRUCTION SET DETAILSAr
Page 244 and 245: word is optional, it is so indicate
Page 246 and 247: Table A-1 Instruction Description N
Page 248 and 249: Table A-1 Instruction Description N
Page 250 and 251: A.4 ADDRESSING MODESThe addressing
Page 252 and 253: Addressing ModeTable A-3 DSP56K Add
Page 254 and 255: Table A-4 Addressing Mode Modifier
Page 256 and 257: S (Scaling Bit)The scaling bit (S)
Page 258 and 259: C (Carry Bit)Set if a carry is gene
Page 260 and 261: The following notes apply to Table
Page 262 and 263: ABS Absolute Value ABSOperation:I D
Page 264 and 265: ACC Add Long with Carry ACCOperatio
Page 266 and 267: ADD Add ADDOperation:S+D-+D (parall
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ADDL Shift Left and Add Accumulator
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ADDR Shift Right and Add Accumulato
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AND Logical AND ANDOperation:S - 0[
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ANDIAND Immediate with Control Regi
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ASL Arithmetic Shift Accumulator Le
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ASR Arithmetic Shift Accumulator Ri
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BCHG Bit Test and Change BCHGOperat
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BCHGBit Test and ChangeBCHGFor othe
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BCHGBit Test and ChangeBCHGInstruct
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BCHGBit Test and Ch~ngeBCHGInstruct
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BCLR Bit Test and Clear BCLROperati
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BCLRBit Test and ClearBCLRFor other
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BCLRBit Test and ClearBCLRInstructi
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BCLRBit Test and ClearBCLRInstructi
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BSET Bit Test and Set BSElOperation
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BSElBit Test and SetBSElFor other d
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BSETBit Test and SetBSETInstruction
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BSETBit Test and SetBSETInstruction
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8TST Bit Test 8TSTOperation:Assembl
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BTSTBit TestBTSTInstruction Format:
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8TSTBit Test8TSTInstruction Format:
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CLR Clear Accumulator CLROperation:
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CMP Compare CMPOperation:Assembler
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CMPM Compare Magnitude CMPMOperatio
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DEBUG Enter Debug Mode DEB,UGOperat
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DEBUGcc Enter Debug Mode Conditiona
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DECDecrement by OneDECOperation:0-1
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DIV Divide Interation DIVOperation:
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DIV Divide Interation DIVExample: (
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DIV Divide Interatlon DIVA complete
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DOStart Hardware LoopDOOperation:As
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DO Start Hardware Loop DOmented by
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DOStart Hardware LoopDOExample:DO #
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DO Start Hardware Loop DOInstructio
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DO Start Hardware Loop DOInstructio
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ENDDO End Current DO Loop ENDDOOper
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EOR Logical Exclusive OR EOROperati
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ILLEGALIllegal Instruction Interrup
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INC Increment by One INCOperation:A
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JccJump ConditionallyJccOperation:I
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Jcc Jump Conditionally JccInstructi
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JCLR Jump If Bit Clear JCLROperatio
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JCLRJump if Bit ClearJCLRInstructio
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JCLRJump if Bit ClearJCLRInstructio
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JMPJumpJMPOperation:Oxxx --t PCea -
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JScc Jump to Subroutine Conditional
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JScc Jump to Subroutine Conditional
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JSCLR Jump to Subroutine If Bit Cle
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JSCLR Jump to Subroutine if Bit Cle
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JSCLRJump to Subroutine if Bit Clea
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JSCLR Jump to Subroutine if Bit Cle
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JSETJump If Bit SetJSETOperation:If
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JSETJump If Bit SetJSETInstruction
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JSETJump if Bit SetJSETInstruction
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JSR Jump to Subroutine JSROperation
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JSSET Jump to Subroutine if Bit Set
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JSSETJump to Subroutine If Bit SetJ
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JSSETJump to Subroutine If Bit SetJ
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LSL Logical ~hlft Left LSLOperation
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LSR Logical Shift Right LSROperatio
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LUALoad Updated AddressLUAOperation
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MAC Signed Multiply-Accumulate MACO
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MACSigned Multiply-AccumulateMACTim
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MACR Signed Multiply-Accumulate and
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MACR Signed Multiply-Accumulate and
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MOVE Move Data MOVEOperation:S~DAss
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MOVE Move Data MOVEParallel Move De
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No Parallel Data MoveOperation:Asse
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IImmediate Short Data MoveIOperatio
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IImmediate Short Data MoveIConditio
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RRegister to Register Data MoveROpe
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R Register to Register Data Move RC
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uAddress Register UpdateuOperation:
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X: X Memory Data Move X:Operation:A
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X: X Memory Data Move X:Instruction
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X: X Memory Data MoveX:Instruction
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X:RX Memory and Register Data MoveX
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X:R X Memory and Register Data Move
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X:R X Memory and Register Data Move
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Y: V Memory Data Move Y:Operation:A
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V: Y Memory Data Move V:Note: The M
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V: Y Memory Data MoveV:Instruction
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R:V Register and V Memory Data Move
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R:Y Register and Y Memory Data Move
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R:VRegister and V Memory Oata MoveR
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L: Long Memory Data Move L:Operatio
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L: Long Memory Data Move L:Instruct
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X: V: xv Memory Data Move X: V:Oper
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X: V: xv Memory Data Move X: V:Note
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MOVEC Move Control Register MOVECOp
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MOVEC Move Control Register MOVECA
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MOVECMove Control RegisterMOVECRegi
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MOVECMove Control RegisterMOVECInst
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MOVEMMove Program MemoryMOVEMOperat
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MOVEM Move Program Memory MOVEMExam
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MOVEM Move Program Memory MOVEMS D
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MOVEP Move Peripheral Data MOVEPOpe
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_______-----'MOVEP Move Peripheral
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MOVEPMove Peripheral DataMOVEPInstr
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MOVEPMove Peripheral DataMOVEPInstr
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MPY Signed Multiply MPYOperation:±
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MPY Signed Multiply MPYInstruction
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MPYR Signed Multiply and Round MPYR
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MPYR Signed Multiply and Round MPYR
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NEG Negate Accumulator NEGOperation
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NOP No Operation NOPOperation:PC+1-
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NORM Normalize Accumulator Iteratio
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NOT Logical Complement NOTOperation
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OR Logical Inclusive OR OROperation
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ORI OR Immediate with Control Regis
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REP Repeat Next Instruction REPOper
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REP Repeat Next Instruction REPExpl
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REPRepeat Next InstructionREPInstru
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REP Repeat Next Instruction REPInst
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RESETReset On-Chip Peripheral Devic
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RND Round Accumulator RNDOperation:
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RND Round Accumulator RNDCondition
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ROL Rotate Left ROLOperation:r47 24
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ROR Rotate Right ROROperation: c:c~
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RTI Return from Interrupt RTIOperat
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RTS Return from Subroutine RTSOpera
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SBC Subtract Long with Carry secOpe
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SBC Subtract Long with Carry SBCCon
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STOP Stop Instruction Processing ST
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SUB Subtract SUBOperation:O-S -4 D
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SUBL Shift Left and Subtract Accumu
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SUBR Shift Right and Subtract Accum
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SWI Software Interrupt SWIOperation
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Tee Transfer Conditionally TeeOpera
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Tee Transfer Conditionally TeeInstr
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TFR Transfer Data ALU Register TFRO
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TST Test Accumulator TSTOperation:A
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WAIT Wait for Interrupt WAITOperati
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A.a INSTRUCTION TIMINGThis section
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cycles that may be required over an
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additional (if any) instruction pro
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3. Evaluate the "ap" term using Tab
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Table A-7 Parallel Data Move Timing
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Table A-12 RTIIRTS Timing SummaryOp
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A.9.1 Restrictions Near the End of
Page 548 and 549:
Immediately before ENDDOBCHG lA, lC
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Immediately before JSCLR from SSH o
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Section A.10.4 gives the encoding f
Page 554 and 555:
Table A-20 Five-Bit Register Encodi
Page 556 and 557:
A.10.2 Instruction Encoding for the
Page 558 and 559:
A.10.3 Instruction Encoding for Ins
Page 560 and 561:
JSETJSET#n,X:ea,xxxx#n,Y:ea,xxxx23
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BCLRBCLR#n,X:pp#n,Y:pp23I 0 0 0 016
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BCLR23#n,O0 0 0 0 1 016 15 871 o \
Page 566 and 567:
DODOX:ea,exprV:ea,expr23 16 15 87 0
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MPYR (±)S,#n,DDEBUGccDEBUG23 16 15
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ILLEGALRTINOP23 16 15 87 0I 0 0 0 0
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Nonmultlply Instruction EncodingThe
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EORS,D23 87 43 0DATA BUS MOVE FIELD
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NOTD23 87 43 0DATA BUS MOVE FIELDSU
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APPENDIX BBENCHMARK PROGRAMS-
Page 581 and 582:
B.1 INTRODUCTIONTable 8-1 provides
Page 583 and 584:
page 132,66,0,6opt rc.*************
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;This program originally available
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page 132,66,0,6opt rc...._..__.....
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page 132,60,1,1;newlms2n.asm; New I
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,; Main program to call the rfft-56
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jle -'oopmove xO,rOmove y1,amove x:
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FirstGrouplnPassdo nO,FirstGrouplnP
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; Real input data are split into tw
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zero (bit 2) .................... 5
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-M- OnCE Commands .................
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Saturation Arithmetic .............
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DSP56K FAMILY INTRODUCTION_DSP56K C
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