section 7 - Index of

chip clock. (Here, T3 is equal to the phase described by the new divide factor plus thetime required to wait for a synchronizing pulse, which is less than 1.5ETc.) For MF>4,such synchronization is not guaranteed and the instruction cycle is not lengthened.If the DFO-DF3 bits are changed by the same instruction that changes the MFO-MF11bits, the LPD divider factor changes before the detection of the change in the multiplicationfactor. This means that the detection of loss of lock will occur after the LPD hasstarted dividing by the new division factor.9.4.6 Loss of LockThe PLL distinguishes between cases where MF>4 and cases where MF~4. If MF~4, thePLL will detect loss of lock if a skew of 2.5 to 4.5 ns develops between the two clockinputs to the phase detector.If MF>4, the PLL will detect loss of lock when there is a discrepancy of one clock cyclebetween the two clock inputs to the phase detector. When either of these two conditionsoccurs, the following also occur:1. PLOCK will be deasserted, indicating that loss of lock condition has occurred.2. The PLL will re-acquire the proper phase/frequency. When lock occurs,PLOCK will be asserted.9.4.7 STOP Processing StateIf the PSTP bit is cleared, executing the STOP instruction will disable the on-chip crystaloscillator and the PLL. In this state the chip consumes the least possible power. Whenrecovering from the STOP state, the recovery time will be 16 or 64k external clock cycles(according to bit 6 in the Operating Mode Register) plus the time needed for the PLL toachieve lock.If the PSTP bit is set, executing the STOP instruction will leave the on-chip crystal oscillator(if XTLD=O) and the PLL loop (if PEN=1) operating, but will disable the clock to theLPD and the rest of the DSP. When recovering from the STOP state, the recovery timewill be only three clock cycles.9.4.8 CKOUT ConsiderationsThe CKOUT clock output is held high while disabled, which is also while the CODO-COD1bits are set. If the CKOUT clock output is low at the moment the CODO-COD1 bits are set,then the CKOUT clock output will complete the low cycle and then be disabled high. If theprogrammer re-enables the CKOUT clock output before it reaches the high logic level duringthe disabling process, the CKOUT operation will be unaffected.