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JSETJump if Bit SetJSETInstruction Format:JSET #n,X:pp,xxxxJSET #n,Y:pp,xxxxOpcode:23 16 15 8 7 00000101 01 10 P P P P P P 11 S 1 b b b b bABSOLUTE ADDRESS EXTENSIONInstruction Fields:#n=bit number=bbbbb,pp=6-bit I/O Short Address=pppppp,xxxx=16-bit Absolute Address in extension word1/0 Short Address pppppp000000•111111Timing: 6+jx oscillator clock cyclesMemory: 2 program wordsMemory SpaceSX Memory 0Y MemoryBit Number bbbbb00000•10111
JSET Jump If Bit Set JSETInstruction Format:JSET #n,S,xxxxOpcode:23 16 15 8700000101 D DDDDDloo 1bbbbbABSOLUTE ADDRESS EXTENSIONInstruction Fields:#n=bit number=bbbbb,S=source register=DDDDDD,xxxx=16-bit Absolute Address in extension wordSource Register4 registers in Data ALU8 accumulators in Data ALU8 address registers in AGU8 address offset registers in AGU8 address modifier registers in AGU8 program controller registersDDDDDDo 0 0 1 D D001 DDD010 TT To 1 1 N N N1 0 0 F F F1 1 1 G G GBit Number bbbbb00000•10111See Section A.1 0 and Table A-18 for specific register encodings.Notes: If A or B is specified as the destination operand, the following sequence of eventstakes place:1. The S bit is computed according to its definition (See Section A.5)2. The accumulator value is scaled according to the scaling mode bits SOand 81 in the status register (SR).3. If the accumulator extension is in use, the output of the shifter is limited tothe maximum positive or negative saturation constant, and the L bit is set.4. The bit test is performed on the resulting 24-bit value, and the jump is takenif the bit tested is set. The original contents of A or B are not changed.Timing: 6+jx oscillator clock cyclesMemory: 2 program words
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DSP56K FAMILY INTRODUCTIONDSP56K CE
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Motorola reserves the right to make
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Table of Contents (Continued)Paragr
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ParagraphNumberTable of Contents (C
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FigureNumberList of Figures (Contin
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List of Tables (Continued)TablePage
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1.1 INTRODUCTIONThe DSP56K family i
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Fewer componentsStable, determinist
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Digital FilteringFinite Impulse Res
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architecture matches the shape of t
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• DSP56001 Compatibility - All me
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SECTION 2DSP56K CENTRAL ARCHITECTUR
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--I«a:w:ca.ffi~a. a.24-Bit 56KModu
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-rectly addressable registers: the
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3.1 DATA ARITHMETIC LOGIC UNITThis
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3.2.1 Data ALU Input Registers (X1,
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"""""" 24 BITS;:~:>~~::~~~:~:~:~:::
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3.2.4 Accumulator ShifterThe accumu
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Table 3-1 Limited Data ValuesDestin
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_--- N BITS ---_TWOS COMPLEMENT INT
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CASE I: IF AO < $800000 (1/2), THEN
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one instruction cycle. The ANDI ins
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3.5 DATA ALU PROGRAMMING MODELThe D
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4.1 ADDRESS GENERATION UNIT AND ADD
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!---LOWADDRESS ALU -----I~.j.I.....
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•••••••• _ ........
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4.4.1 Address Register Indirect Mod
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EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
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EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
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EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
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Table 4-2 Address Modifier SummaryM
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ADDRESS -f-_POINTERUPPER BOUNDARYiM
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EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
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oundary gives a 16-bit binary numbe
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4.4.2.4 Address-Modifier-Type Encod
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SECTION 5PROGRAM CONTROL UNIT-
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X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
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interruptible since they are fetche
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PROGRAM CONTROL UNIT-23 1615 023 16
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The GGR is a special purpose contro
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If S 1 =0 and SO=O (no scaling)then
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-23 876543210I * 1* JSO I * I Mel y
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5.4.5.1 Stack Pointer (Bits 0-3)The
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-DATA ARITHMETIC LOGIC UNITINPUT RE
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6.1 INSTRUCTION SET INTRODUCTIONThe
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shown in Figure 6-2. Most instructi
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23 87 0L...-I ___-'-I_---'I BUS~ LS
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The MR and CCR may be accessed indi
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6.3.4 Operand ReferencesThe DSP sep
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Some address register indirect mode
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EXAMPLE A: IMMEDIATE INTO 24-BIT RE
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EXAMPLE A: IMMEDIATE SHORT INTO AO,
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EXAMPLE A: MOVE P: $3200,XOBEFORE E
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Table 6-1 Addressing Modes SummaryA
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6.4.2 LogicallnstructlonsThe logica
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START OF LOOP1)SP+ 1 • SP; LA. SS
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OPCODE/OPERANDSPARALLEL MOVE EXAMPL
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SECTION 7PROCESSING STATES-
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Each instruction requires a minimum
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second instruction of the downloade
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The DO instruction is another instr
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SP and SSH/SSL register manipulatio
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7.3.1 Interrupt TypesThe DSP56K rel
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Table 7-2 Status Register Interrupt
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7.3.3 Interrupt SourcesInterrupts c
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interrupts makes it very useful for
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MAINPROGRAMFETCHESLONG INTERRUPTSER
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7.3.3.3 Other Interrupt SourcesOthe
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7.3.4 Interrupt ArbitrationInterrup
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7.3.7 Interrupt Instruction Executi
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MAINPROGRAMMEMORYINTERRUPT SYNCHRON
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MAINPROGRAMFETCHESINTERRUPTSYNCHRON
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MAINPROGRAMFAST INTERRUPTVECTORLONG
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MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
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7.5 WAIT PROCESSING STATEThe WAIT i
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The stop processing state halts all
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the first instruction fetch). If th
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RESET -----------------------------
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16 - BIT INTERNALADDRESS BUSESX ADD
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8.2.2.1 Address (AO-A15)These three
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SECTION 9PLL CLOCK OSCILLATOR-
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X MEMORYRAM/ROMEXPANSION24-Bit56KMo
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23 22 21 20 19 18 17 16 15 14 13 12
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cleared. To enable rapid recovery w
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-CLVCCVCC for the CKOUT output. The
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4. For all input frequencies which
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While the PLL is regaining lock, th
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10.1 ON-CHIP EMULATION INTRODUCTION
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10.2.2 Debug Serial Clock/Chip Stat
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76543210I R/W I GO I EX I RS41 RS31
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shifted in (so a new command is ava
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10.3.4.4 Software Debug Occurrence
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10.4.4 Memory High Address Comparat
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10.6.1 External Debug Request Durin
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PABCIRCULARBUFFERPOINTERDSCKDSOFigu
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are serially available to the exter
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k. ACKI. ClKm. Send command READ FI
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19. ACK20. Send command READ GDB RE
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10.11.6.1 Case 1: Return To The Pre
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SECTION 11ADDITIONAL SUPPORTDr. BuB
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The following is a partial list of
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• In-line assembler language code
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I Document 10 I Version Synopsis I
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I Document ID I Version Synopsis I
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11.5 MOTOROLA DSP NEWSThe Motorola
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DIGITAL SIGNAL PROCESSINGAlan V. Op
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C Programming Language:Controls:. C
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Image Processing:DIGITAL IMAGE PROC
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LINEAR PREDICTION OF SPEECHJ. D. Ma
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A.1 APPENDIX A INTRODUCTIONThis app
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XnYnTable A-1 Instruction Descripti
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Table A-1 Instruction Description N
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Table A-1 Instruction Description N
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Table A-2 DSP56K Addressing ModesAd
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The address register indirect addre
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A.SCONDITION CODE COMPUTATION15 14
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S1 SO Scaling Mode Signed Integer P
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Table A-5 Condition Code Computatio
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A.7 INSTRUCTION DESCRIPTIONSThe fol
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ABSAbsolute ValueABSInstruction For
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ADC Add Long with Carry ADCresult.
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ADD Add ADDCondition Codes:15 14 13
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ADDL Shift Left and Add Accumulator
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ADDR Shift Right and Add Accumulato
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ANDLogical ANDANDInstruction Format
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ANDIAND Immediate with Control Regi
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ASL Arithmetic Shift Accumulator Le
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ASR Arithmetic Shift Accumulator Ri
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BCHG Bit Test and Change BCHGExplan
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BCHGBit Test and ChangeBCHGInstruct
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BCHGBit Test and ChangeBCHGInstruct
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BCHG Bit Test and Change BCHGNotes:
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BCLR Bit Test and Clear BCLRExplana
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BClRBit Test and ClearBClRInstructi
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BClRBit Test and ClearBClRInstructi
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BClR Bit Test and Clear BClRNotes:
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BSET Bit Test and Set BSETExplanati
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BSETBit Test and SetBSETInstruction
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BSETBit Test and SetBSETInstruction
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BSET Bit Test and Set BSETNotes: If
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BTSTBit TestBTSTCondition Codes:115
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8TSTBit Test8TSTInstruction Format:
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8TSTBit Test8TSTInstruction Format:
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CLRClear AccumulatorCLRInstruction
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CMP Compare CMPCondition Codes:15 1
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CMPM Compare Magnitude CMPMConditio
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DEBUGEnter Debug ModeDEBUGOpcode:23
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DEBUGcc Enter Debug Mode Conditiona
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DEC Decrement by One DECInstruction
Page 323 and 324: DIV Divide Interation DIVThe DIV in
Page 325 and 326: DIV Divide Interation DIVNote that
Page 327 and 328: DIVInstruction Format:DIV S,DDivide
Page 329 and 330: DO Start Hardware Loop DOexecuted 6
Page 331 and 332: DOStart Hardware LoopDOAt LAOther R
Page 333 and 334: DOStart Hardware LoopDOInstruction
Page 335 and 336: DOStart Hardware LoopDOInstruction
Page 337 and 338: DO Start Hardware Loop DONotes: If
Page 339 and 340: ENDDO End Current DO Loop ENDDOExpl
Page 341 and 342: EOR Logical Exclusive OR EORInstruc
Page 343 and 344: ILLEGALIllegal Instruction Interrup
Page 345 and 346: INC Increment by One INCInstruction
Page 347 and 348: Jcc Jump Conditionally JccRestricti
Page 349 and 350: JccJump ConditionallyJccEffectiveAd
Page 351 and 352: JCLR Jump If Bit Clear JCLRRestrict
Page 353 and 354: JCLRJump If Bit ClearJCLRInstructio
Page 355 and 356: JCLR Jump If Bit Clear JCLRInstruct
Page 357 and 358: JMPJumpJMPInstruction Fields:xxx=12
Page 359 and 360: JSccJump to Subroutine Conditionall
Page 361 and 362: JScc Jump to Subroutine Conditional
Page 363 and 364: JSCLR Jump to Subroutine if Bit Cle
Page 365 and 366: JSCLRJump to Subroutine If Bit Clea
Page 367 and 368: JSCLRJump to Subroutine If Bit Clea
Page 369 and 370: JSCLR Jump to Subroutine If Bit Cle
Page 371 and 372: JSET Jump if Bit Set JSETRestrictio
Page 373: JSETJump if Bit SetJSETInstruction
Page 377 and 378: JSR Jump to Subroutine JSRInstructi
Page 379 and 380: JSSET Jump to Subroutine if Bit Set
Page 381 and 382: JSSETJump to Subroutine if Bit SetJ
Page 383 and 384: JSSET Jump to Subroutine if Bit Set
Page 385 and 386: LSL Logical Shift Left LSLCondition
Page 387 and 388: LSR Logical Shift Right LSRConditio
Page 389 and 390: LUALoad Updated AddressLUACondition
Page 391 and 392: MAC Signed Multiply-Accumulate MACC
Page 393 and 394: MACSigned Multiply-AccumulateMACTim
Page 395 and 396: MACR Signed Multiply-Accumulate and
Page 397 and 398: MACR Signed MUltiply-Accumulate and
Page 399 and 400: MOVE Move Data MOVEExplanation of E
Page 401 and 402: MOVE Move Data MOVEWhen a 56-bit ac
Page 403 and 404: No Parallel Data MoveInstruction Fo
Page 405 and 406: I Immediate Short Data Move IExampl
Page 407 and 408: I Immediate Short Data Move IDDD d
Page 409 and 410: R Register to Register Data Move RE
Page 411 and 412: R Register to Register Data Move RI
Page 413 and 414: uAddress Register UpdateuInstructio
Page 415 and 416: X: X Memory Data Move X:Note:Due to
Page 417 and 418: X: X Memory Data Move X:S D DS,D d
Page 419 and 420: X: X Memory Data Move X:S D DS,D d
Page 421 and 422: X:R X Memory and Register Data Move
Page 423 and 424: X:R X Memory and Register Data Move
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X:R X Memory and Register Data Move
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Y: Y Memory Data Move Y:Note: This
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Y: Y Memory Data Move Y:S D DS,D d
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Y: Y Memory Data Move Y:S D DS,D d
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R:V Register and V Memory Data Move
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R:V Register and Y Memory Data Move
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R:V Register and Y Memory Data Move
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L: Long Memory Data Move L:Example:
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L: Long Memory Data Move L:Instruct
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X: Y: xv Memory Data Move X: Y:Exam
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X: Y: xv Memory Data Move X: Y:S1 D
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MOVEC Move Control Register MOVECst
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MOVEC Move Control Register MOVECCo
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MOVECMove Control RegisterMOVECInst
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MOVEC Move Control Register MOVECTi
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MOVEM Move Program Memory MOVEMoper
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MOVEM Move Program Memory MOVEMInst
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MOVEMMove Program MemoryMOVEMInstru
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MOVEP Move Peripheral Data MOVEPist
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MOVEP Move Peripheral Data MOVEPCon
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MOVEP Move Peripheral Data MOVEPIns
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MOVEP Move Peripheral Data MOVEPIns
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MPY Signed Multiply MPYExplanation
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MPY Signed Multiply MPYInstruction
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MPYR Signed Multiply and Round MPYR
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MPYR Signed Multiply and Round MPYR
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NEGNegate AccumulatorNEGInstruction
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NOPNo OperationNOPInstruction Forma
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NORM Normalize Accumulator Iteratio
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NOTLogical ComplementNOTInstruction
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ORLogical Inclusive ORORInstruction
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ORI OR Immediate with Control Regis
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REP Repeat Next Instruction REPRest
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REPRepeat Next InstructionREPInstru
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REPRepeat Next InstructionREPInstru
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REP Repeat Next Instruction REPNote
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RESETReset On-Chip Peripheral Devic
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RND Round Accumulator RNDConvergent
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RNDRound AccumulatorRNDInstruction
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ROL Rotate Left ROLCondition Codes:
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ROR Rotate Right RORCondition Codes
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RTIReturn from InterruptRTIConditio
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RTSReturn from SubroutineRTSInstruc
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sec Subtract Long with Carry secExp
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secSubtract Long with CarrysecInstr
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STOPStop Instruction ProcessingSTOP
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SUB Subtract SUBCondition Codes:S -
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SUBL Shift Left and Subtract Accumu
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SUBR Shift Right and Subtract Accum
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SWISoftware InterruptSWICondition C
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Tee Transfer Conditionally Teetion
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Tee Transfer Conditionally TeeInstr
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TFR Transfer Data ALU Register TFRC
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TSTTest AccumulatorTSTInstruction F
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WAIT Wait for Interrupt WAITConditi
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including the number of words per i
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5. Compute final results.Thus, base
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JLC (R2+N2)will requireand will exe
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Table A-6 Instruction Timing Summar
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Note that the "ap" term in Table A-
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Table A-14 Memory Access Timing Sum
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Other RestrictionsDO SSH,xxxxJSR to
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Immediately before MOVEC from SSH o
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A.9.S REP RestrictionsThe REP instr
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Table A-18 Triple-Bit Register Enco
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Table A-24 Program Control Unit Reg
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R: Register to Register Parallel Da
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JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
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JSSET#n,S,xxxx23 16 15 87 000001011
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BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
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MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
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LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
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ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
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Table A-28 Operation Code QQQ Decod
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Table A-30 Special Case #10 P E R C
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NEGD23 87 43 0DATA BUS MOVE FIELDLS
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ADDRS,D23 87 43 oDATA BUS MOVE FIEL
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lEI
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Table 8-1 27-MHz Benchmark Results
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.*._---*-----*-------**-------....
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;Latest Revision - September 30, 19
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All coefficients are divided by 2:w
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Real input FFT based on Glenn Bergl
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countountcountcountorg y:coefset 0d
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; Real-Valued FFT for MOTOROLA DSP5
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; first group in the last passmove
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A Accumulator ....... ' ...........
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-H- fast ..........................
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PGND ..............................
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DSP56K FAMILY INTRODUCTIONDSP56K CE
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