section 7 - Index of

Table A-14 Memory Access Timing SummaryAccess XMem YMem PMemType Access Access AccessX: Int - -X: Ext - -Y: - Int -Y: - Ext -P: - - IntP: - - ExtliD: - - -liD: - - -L:XY: Int Int -L:XY: Int Ext -L:XY: Ext Int -L:XY: Ext Ext -Note 1: wx = external X memory access wait stateswy = external Y memory access wait stateswp = external P memory access wait stateswio = external 110 memory access wait statesI/O +ax +ay +apAccess Cycle Cycle Cycle- 0 - -- wx - -- - 0 -- - wy -- - - 0- - - wpInt - - -Ext - - -- - - -- - - -- - - -- - - -Note 2: wx, wy, wp, and wio are programmable from 0 - 15 wait states in the port A bus control register (BCR).+aloCycle------0wio----+axyCycle--------0wywx2+wx+wyA.9 INSTRUCTION SEQUENCE RESTRICTIONSDue to the pipelined nature of the DSP56K central processor, there are certain instructionsequences that are forbidden and will cause undefined operation. Most of theserestricted sequences would cause contention for an internal resource, such as the stackregister. The DSP assembler will flag these as assembly errors.Most of the following restrictions represent very unusual operations which probablywould never be used but are listed only for completeness.Note: The DSP56K macro assembler is designed to recognize all restrictions and flagthem as errors at the source code level. Since many of these are instruction sequencerestrictions, they cannot be flagged as errors at the object code level such as when usingthe DSP56K simulator's single-line assembler. Therefore, if any changes are made atthe object code level using the simulator, the user should always re-assemble his programat the source code level using the DSP56K macro assembler to verify that norestricted instruction sequences have been generated.-