Model 7002Switch System Instruction Manual - Advanced Test ...

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IEEE-488 ReferenceStandard Event Status Register — This is a latched readonly register that is used to record the occurrence of standardevents. Each used bit in the register represents a standardevent. Descriptions of these standard events are provided inparagraph 5.10.4.When a standard event occurs, the appropriate bit in theStandard Event Status Register sets. For example, if you attemptto read data from an empty Output Queue, a Query Error(QYE) will occur and set bit B2 of the status register. Aset bit in this register will remain set until an appropriate operationis performed to clear the register. The Standard EventStatus Register can be read at any time by using the followingcommon query command (see paragraph 5.10.4 for details):*ESR?Reading this register using the *ESR? command also clearsthe register. The following list summarizes all operations thatclear the Standard Event Status Register:1. Cycling power.2. Sending the *CLS common command.3. Sending the *ESR? common command.corresponding set bit in the Standard Event Status EnableRegister. The logic “1” output of the AND gate is applied tothe input of the OR gate and thus, sets the ESB bit in the StatusByte Register.The individual bits of the Standard Event Status Enable Registercan be set or cleared by using the following commoncommand (see paragraph 5.10.2):*ESE The Standard Event Status Enable register can be read at anytime by using the following common query command (seeparagraph 5.10.3 for details):*ESE?Reading this register using the *ESE? command does notclear the register. The following list summarizes all operationsthat will clear the Standard Event Status Enable Register:1. Cycling power.2. *ESE 0Standard Event Status Enable Register — This register isprogrammed by the user and serves as a mask for standardevents. When a standard event is masked, the occurrence ofthat event will not set the Event Summary Bit (ESB) in theStatus Byte Register. Conversely, when a standard event isunmasked, the occurrence of that event will set the ESB bit.A bit in the Standard Event Status Register is masked whenthe corresponding bit in the Standard Event Status EnableRegister is cleared (0). When the masked bit of the StandardEvent Status Register sets, it is ANDed with the correspondingcleared bit in the Standard Event Status Enable Register.The logic “0” output of the AND gate is applied to the inputof the OR gate and thus, will not set the ESB bit in the StatusByte Register.5.6.2 Operation event statusThe reporting of operation events is controlled by a set of 16-bit registers; the Operation Condition Register, the TransitionFilter, the Operation Event Register, and the OperationEvent Enable Register. Figure 5-7 shows how these registersare structured.Notice in Figure 5-5 that bits B5 (Waiting in Trigger Layer)and B6 (Waiting in An Arm Layer) of the Operation ConditionRegister are controlled by the arm register set and thetrigger set and the trigger register set (see paragraph 5.6.3and 5.6.5 for details). Each of the bits that is used in theseregisters represents an operation event. Descriptions of theoperation event bits are provided in paragraph 5.16.A bit in the Standard Event Status Register is unmaskedwhen the corresponding bit in the Standard Event Status EnableRegister is set (1). When the unmasked bit of the StandardEvent Status Register sets, it is ANDed with theThe operation status registers are controlled by the:STATus:OPERation commands in the :STATus subsystem(see paragraph 5.16).5-9
IEEE-488 ReferenceTo OperationSummary Bit(OSB) of StatusByte Register.(See Figure 5-11).ORFrom OR’ed summary ofArm Event status(see Figure 5-8 in the7002 Instruction Manual).From OR’ed summary ofTrigger Event status(see Figure 5-10 in the7002 Instruction Manual).Idle(B10)Arm(B6)(B15 - B11) (B9) (B8) (B7) (B4) (B3) (B2) (B0)Trig(B5)Set(B1)Operation EventCondition RegisterIdleArm(B15 - B11) (B10) (B9) (B8) (B7) (B6) (B5) (B4) (B3) (B2) (B1) (B0)TrigSetPTR TransitionNTR FilterIdle(B10)Arm(B6)(B15 - B11) (B9) (B8) (B7) (B4) (B3) (B2) (B0)Trig(B5)Set(B1)Operation EventStatus Register&&&&Idle(B10)Arm(B6)(B15 - B11) (B9) (B8) (B7) (B4) (B3) (B2) (B0)Trig(B5)Set(B1)Operation EventStatus EnableRegisterIdle = IdleArm = Waiting in an Arm LayerTrig = Waiting in Trigger LayerSet = Settling& = Logical ANDOR = Logical ORPTR = Positive Transition FilterNTR = Negative Transition FilterFigure 5-7Operation event statusOperation Condition Register — This is a real-time 16-bitread-only register that constantly updates to reflect the currentoperating conditions of the Model 7002. For example,when the instrument is in idle, bit B10 (Idle) of this registerwill be set. When the instrument leaves the idle state, bit B10will clear.The following SCPI query command can be used to read theOperation Condition Register:The Operation Condition Register and the Transition Filterare used to set the bits of the Operation Event Register. TheTransition Filter is discussed next.Operation Transition Filter — The transition filter is madeup of two 16-bit registers that are programmed by the user. Itis used to specify which transition (0 to 1, or 1 to 0) in theOperation Condition Register will set the corresponding bitin the Operation Event Register.:STATus:OPERation:CONDition?5-10
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®Established 1981Advanced Test Equ
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WARRANTYKeithley Instruments, Inc.
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Manual Print HistoryThe print histo
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If you are using a test fixture, ke
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Table of Contents1 General Informat
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4.10.3 Scanning examples ..........
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5.13.4 :FCHannels ................
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List of Illustrations2 Card Install
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6 Theory of OperationFigure 6-1 Mod
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8 MaintenanceTable 8-1Table 8-2Tabl
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General Informationthorized repair
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Card InstallationNOTEIf using the s
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3Getting Started3.1 IntroductionThi
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Getting StartedWARNING: INTERCONNEC
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Getting StartedSLOT 112ROW34COLUMN
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Getting Started3.6 Overview of scan
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Getting Started3.7.2 Close and open
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Getting Started2. If the scan list
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Getting Started3.8 Switching card c
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Getting Started3.9.2 Close and Open
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Getting StartedSCPI (Standard Comma
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Getting Started3.10.5 Abbreviated s
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Getting Started20 OUTPUT 707; “:s
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4Front Panel Operation4.1 Introduct
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Front Panel OperationAnnunciatorsTa
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Front Panel Operation3COLUMNSLOT 1
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Front Panel OperationNot all Model
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Front Panel Operationthe VFD which
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Front Panel OperationFront panel ke
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Front Panel OperationSlot 111 2 3 4
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Front Panel Operation4.8 Channel li
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Front Panel OperationStep 3. Enter
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Front Panel Operationd. Click the I
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Front Panel OperationIdleOPEN ALLId
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Front Panel OperationChannel layerN
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Front Panel Operationsatisfy a chan
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Front Panel OperationExample 3:ARM
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Front Panel Operation6. To store th
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Page 120 and 121: 5IEEE-488 Reference5.1 Introduction
Page 122 and 123: IEEE-488 ReferenceIEEE-488Table 5-1
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Page 156 and 157: IEEE-488 Referenceas command paths.
Page 158 and 159: IEEE-488 ReferenceResponse messages
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Page 162 and 163: IEEE-488 Reference5.10.1 *CLS ⎯ c
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Page 170 and 171: IEEE-488 ReferenceNOTESee *OPC?, *T
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IEEE-488 Reference5.10.12 *SRE ⎯
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IEEE-488 Reference5.10.13 *SRE? ⎯
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IEEE-488 ReferenceBit 5, Event Summ
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IEEE-488 Reference5.10.16 *TST? ⎯
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IEEE-488 ReferenceLine 70 Wait unti
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IEEE-488 ReferenceSCPI command subs
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IEEE-488 Reference5.11 :DISPlay sub
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:DISPlay subsystemIEEE-488 Referenc
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:DISPlay subsystemIEEE-488 Referenc
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IEEE-488 Reference5.12 :OUTPut subs
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IEEE-488 Reference5.13 [:ROUTe] sub
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[:ROUTe] subsystemIEEE-488 Referenc
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IEEE-488 Reference5.14 Sense subsys
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IEEE-488 Reference5.15 :SOURce subs
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IEEE-488 Reference5.16 :STATus subs
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:STATus SubsystemIEEE-488 Reference
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IEEE-488 Reference5.17 :SYSTem subs
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:SYSTem SubsystemIEEE-488 Reference
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IEEE-488 Reference5.18 Trigger subs
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Trigger subsystemIEEE-488 Reference
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6Theory of Operation6.1 Introductio
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Theory of Operation6.3 Control func
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Theory of Operation6.4 Relay contro
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Theory of OperationID data is conta
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Theory of OperationFromDigitalBoard
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Theory of Operationµ DINConnectorT
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MaintenanceNOTEThe digital and disp
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MaintenanceFuse replacement procedu
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Maintenance7.6 Instrument disassemb
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Maintenance7.6.5 Power supplies rem
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Maintenance8. Press “1”, “1
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MaintenanceEDIT ERR REM TALK LSTN S
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MaintenanceTo review the error, pre
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MaintenanceTrigger 8 (STI8) is set
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MaintenanceDETAIL AREF:GRN/YELWIRE#
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MaintenanceBOARDS MUST BE HANDLED W
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MaintenanceSTEP 1FA-151-1, FASTENER
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MaintenanceDETAIL ACC-47, CABLEDIG
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Maintenance8#4-40x1/4"PFH(4 REQ'D)(
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Replaceable Parts
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Replaceable Parts
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Replaceable PartsTable 8-2Digital b
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Artisan Scientific - Quality Instru
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(+5V)**(+5V)**** ****** **********
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Replaceable PartsTable 8-3VFD displ
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Replaceable PartsTable 8-4Backplane
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Artisan Scientific - Quality Instru
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Replaceable Parts
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Replaceable PartsTable 8-6Miscellan
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Interface Function CodesTable A-1Mo
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Controller ProgramsIBM PC/XT/AT wit
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Controller Programs10 DEF SEG=&HC40
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Controller ProgramsHewlett-Packard
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Controller ProgramsBUS.INIT\ Initia
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CASCII Character Codesand IEEE-488
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ASCII Character Codes and IEEE-488M
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IEEE-488 Bus Overviewtype of instru
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IEEE-488 Bus Overviewdevice will re
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IEEE-488 Bus OverviewLAG (Listen Ad
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IEEE-488 Bus OverviewTable D-2Hexad
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EIEEE-488 Conformance InformationIn
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FSCPI Conformance InformationIntrod
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SCPI Conformance InformationTable F
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IEEE-488.2 Common CommandsMnemonic
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SCPI Command SubsystemTable H-1DISP
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SCPI Command SubsystemTable H-4SENS
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SCPI Command SubsystemTable H-6 (co
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SCPI Command SubsystemTable H-8 (co
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QuickBasic and QuickC ProgramsMicro
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QuickBasic and QuickC ProgramsMicro
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Index:ABORt 5-134:BBMake 5-88:CLOS
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Scanning channels 4-20Scanning exam
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Specifications are subject to chang
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