Model 7002Switch System Instruction Manual - Advanced Test ...

IEEE-488 ReferenceReading this register using the above SCPI command doesnot clear the register. The following list summarizes operationsthat will clear the Operation Event Enable Register:1. Cycling power.2. Sending the :STATus:PRESet command.3. Sending the :STATus:OPERation:ENABle 0 command.Arm Event Register, and the Arm Event Enable Register.Figure 5-8 shows how these registers are structured. Noticein Figure 5-5 that bit B1 (In An Arm Layer) of the Arm ConditionRegister is controlled by the sequence event registerset (see paragraph 5.6.4 for details). In general, bit B1 setswhen the instrument is in the arm layer (Arm Layer 1) orscan layer (Arm Layer 2) of operation. An explanation of theoperation process over the bus is provided in paragraph 5.7.5.6.3 Arm event statusThe reporting of the arm event is controlled by a set of 16-bitregisters; the Arm Condition Register, the Transition Filter,The various registers used for arm event status are describedas follows: Note that these registers are controlled by the:STATus:OPERation:ARM commands of the :STATus subsystem(see paragraph 5.16).From ORedSummary ofSequence EventStatus (SeeFigure 5-9).AlwaysZeroSeq1(B15) (B14 - B2) (B1) (B0)0Arm EventCondition RegisterSeq1(B15) (B14 - B2) (B1) (B0)0PTRNTRArm EventTransition FilterSeq1(B15) (B14 - B2) (B1) (B0)0Arm EventStatus RegisterOR&&To Waiting for ArmBit (Arm) of OperationEvent Condition Register(See Figure 5-7).Seq1(B15) (B14 - B2) (B1) (B0)Arm Event StatusEnable RegisterSeq 1 = Sequence 1 (Set bit indicates that the7002 is in an arm layer)& = Logical ANDOR = Logical ORPTR = Positive Transition RegisterNTR = Negative Transition RegisterFigure 5-8Arm event status5-12