Model 7002Switch System Instruction Manual - Advanced Test ...

IEEE-488 ReferenceANDed with the bits of the Sequence Event Enable Registerand applied to an OR gate. The output of the OR gate is appliedto bit B1 of the Arm Condition Register (see paragraph5.6.3). The following SCPI query command can be used toread the Sequence Event Register::STATus:OPERation:ARM:SEQuence?Reading this register using the above SCPI command clearsthe register. The following list summarizes all operations thatwill clear the Sequence Event Register:1. Cycling power.2. Sending the *CLS common command.3. Sending the :STATus:OPERation:ARM:SEQuence?query command.Sequence Event Enable Register — This register isprogrammed by the user and serves as a mask for theSequence Event Register. When masked, a set bit in theSequence Event Register will not set bit B1 of the ArmCondition Register. Conversely, when unmasked, a set bit inthe Sequence Event Register will set the bit B1 of the ArmCondition Register.A bit in the Sequence Event Register is masked when thecorresponding bit in the Sequence Event Enable Register iscleared (0). When the masked bit of the Sequence Event Registersets, it is ANDed with the corresponding cleared bit inthe Sequence Event Enable Register. The logic “0” output ofthe AND gate is applied to the input of the OR gate and thus,will not set bit B1 of the Arm Condition Register.A bit in the Sequence Event Register is unmasked when thecorresponding bit in the Sequence Event Enable Register isset (1). When the unmasked bit of the Sequence Event Registersets, it is ANDed with the corresponding set bit in theSequence Event Enable Register. The logic “1” output of theAND gate is applied to the input of the OR gate and thus, willset bit B1 of the Arm Condition Register.The following SCPI query command can be used to read theSequence Event Enable Register::STATus:OPERation:ARM:SEQuence:ENABle?Reading this register using the above SCPI command willnot clear the register. The following list summarizes operationsthat will clear the Sequence Event Enable Register:1. Cycling power.2. Sending the :STATus:OPERation:ARM:SEQuence:EN-ABle 0 command.5.6.5 Trigger event statusThe reporting of the trigger event is controlled by a set of 16-bit registers; the Trigger Condition Register, the TransitionFilter, the Trigger Event Register, and the Trigger Event EnableRegister. Figure 5-10 shows how these registers arestructured.Bit B1 (Seq1) of the register set is used for the trigger event(In Trigger Layer). In general, Bit B1 sets when the instrumentis in (or has exited) the measure layer of operation. Anexplanation of the Model 7002 operation process is providedin paragraph 5.7. The various registers used for trigger eventstatus are described as follows: Note that these registers arecontrolled by the :STATus:OPERation:TRIGger commandsof the :STATus subsystem (see paragraph 5.16).Trigger Condition Register — This is a real-time 16-bitread-only register that constantly updates to reflect the triggerlayer status of the instrument. If bit B1 is set, the instrumentis in the trigger layer (measure layer) of operation.The following SCPI query command can be used to read theTrigger Condition Register::STATus:OPERation:TRIGger:CONDition?The individual bits of the Sequence Event Enable Registercan be set or cleared by using the following SCPI command::STATus:OPERation:ARM:SEQuence:ENABle The Trigger Condition Register and the Transition Filter areused to set bit B1 of the Trigger Event Register. The TransitionFilter is discussed next.5-16