Model 7002Switch System Instruction Manual - Advanced Test ...

MaintenanceThe IEEE-488 interface in the Model 7002 consists of the9914 GPIB chip (U106), and the 75160 (U102) and 75161(U101) bus drivers. The 75160 buffers DIO1-8 data lines, the75161 buffers the bus handshake lines and other control signals.The circuitry to test these parts is contained in the 5064ASIC (U103).Test 104.1 ⎯ Handshake TestFailure of Test 104.1 suggests a digital board error.Circuitry in the 5064 is set up to simulate an IEEE-488 handshake.Bytes are written to the 9914 Data Out register (U106)and the interrupt status register is checked to verify that aByte-Out handshake is completed.These tests verify the basic functionality of the 9914, 75161,and the handshake portion of the ASIC (Signals BNRFD,BNDAC, and BDAV). Failures may indicate that a part is defective,or that the PC board is faulty. Check U101, U103,U106.Test 104.2 ⎯ IEEE-DataFailure of Test 104.2 suggests a digital board error.Bytes are written to the 9914 Data Out register (U106) todrive and release bus line DIO1. The state of this signal isverified at the 68302 through PB0 (BITB1).These tests verify the basic functionality of the 9914 and75160. Failures may indicate that a part is defective or thatthe PC board is faulty. Check U102 and U106.Test 105 ⎯Trigger testsFailure of Test 105 suggests a digital board error.Triggers in the Model 7002 are controlled by circuitry in the5064 ASIC (U103). This part has seven trigger outputs(STO1-STO7) and eight trigger inputs (STI1-STI8).The system trigger bus is controlled by STI1-STI6 andSTO1-STO6.STO7 is connected to the CHANNEL READY BNC connector.STI7 is connected to the EXTERNAL TRIGGER BNCconnector.STI8 is connected to the Group Execute Trigger signal(GET) of the 9914 IEEE-488 bus controller (U106).Tests 105.1-105.6 ⎯ System Trigger BusFailure of Tests 105.1-105.6 suggests a digital board error.System trigger inputs are normally pulled up to +5V throughprotection diodes and 1kΩ resistors (CR102-107, R108,R110, R112, R114, R117, R118). The Model 7002 may generatea trigger on any of the six trigger bus inputs by turningon a FET (Q100-105) controlled by the associated systemtrigger output pin (STO) of the ASIC.In Test 105.1, STI1 is set up as the trigger input. The trigger1 FET is then turned on and off through STO1, and it is verifiedthat this trips the trigger circuitry in the ASIC. This testis then repeated for triggers 2-6 in tests 105.2 - 105.6.Success indicates proper operation of the trigger bus. A faultmay indicate a defective ASIC, FET, diode, resistor, or opencircuitboard trace.Test 105.7 ⎯ External Trigger/Channel ReadyFailure of Test 105.7 suggests a digital board error.This test is similar to System Trigger Tests 105.1-105.6except that there is no internal connection between EXTER-NAL TRIGGER and CHANNEL READY. Consequently,the meaning of a fault is reversed from that of Tests 105.1-105.6, i.e., a fault is registered if a trigger does occur. Thiswould indicate that a short exists between EXTERNALTRIGGER and CHANNEL READY. This fact may be usedto test the external BNC connectors. By shorting CHANNELREADY to EXTERNAL TRIGGER with a BNC cable, Test105.7 should fail. If it does not, the signal path is faulty.Test 105.8 ⎯ Group Execute Trigger (GET)Failure of Test 105.8 suggests a digital board error.7-15