Model 7002Switch System Instruction Manual - Advanced Test ...

IEEE-488 ReferenceReading this register using the above CPI command does notclear the register. The following list summarizes operationsthat will clear the Questionable Event Enable Register:1. Cycling power.2. Sending the :STATus:PRESet command.3. Sending the :STATus:QUEStionable:ENABle 0 command.5.6.7 QueuesThe Model 7002 uses two queues; the Output Queue and theError/Status Queue. The queues are first-in first-out (FIFO)registers. They are used to hold data messages and error/statusmessages respectively. The Model 7002 Status Model(Figure 5-5) shows how the two queues are structured withthe other registers.Output Queue ⎯ The Output Queue is used to hold all datathat pertains to the normal operation of the instrument. Forexample, when a query command is sent, the data messagethat pertains to that query is placed in the Output Queue.When a data message is placed in the Output Queue, theMessage Available (MAV) bit in the Status Byte Register becomesset. A data message is cleared from the Output Queuewhen it is read. The Output Queue is considered clearedwhen it is empty. An empty Output Queue clears the MAVbit in the Status Byte Register.A message from the Output Queue is read by addressing theModel 7002 to talk. The following programming example inHP BASIC 4.0 sends a query command, sends the data messageto the computer, and then displays it on the CRT.10 OUTPUT 707; “*IDN?” ! Request identificationcode20 ENTER 707; A$ ! Address 7002 to talk30 PRINT A$ ! Display ID code40 ENDError Queue ⎯ The Error Queue is used to hold error messagesand status messages. When an error or status event occurs,a message that defines the error/status is placed in theError Queue. This queue will hold up to 10 messages.When a message is placed in the Error Queue, the ErrorAvailable (EAV) bit in the Status Byte Register is set. An errormessage is cleared from the Error Queue when it is read.The Error Queue is considered cleared when it is empty. Anempty Error Queue clears the EAV bit in the Status ByteRegister.An error message from the Error Queue is read by sendingeither of the following SCPI query commands and then addressingthe Model 7002 to talk::SYSTem:ERRor?:STATus:QUEue?Refer to paragraphs 5.16.7 (:STATus:QUEue?) and 5.17.4(:SYSTem:ERRor?) for complete information on reading errormessages.5.6.8 Status byte and service request (SRQ)Service request is controlled by two 8-bit registers; the StatusByte Register and the Service Request Enable Register. Thestructure of these registers is shown in Figure 5-12.Status Byte Register — The summary messages from thestatus registers and queues are used to set or clear the appropriatebits (B2, B3, B4, B5 and B7) of the Status Byte Register.These bits do not latch and their states (0 or 1) are solelydependent on the summary messages (0 or 1). For example,if the Standard Event Status Register is read, its register willclear. As a result, its summary message will reset to 0, whichin turn will clear the ESB bit in the Status Byte Register.Bit B6 in the Status Byte Register is either:• The Master Summary Status (MSB) bit, sent in responseto the *STB? command, indicates the statusof any set bits with corresponding enable bits set.5-21