Model 7002Switch System Instruction Manual - Advanced Test ...

IEEE-488 ReferenceArm Condition Register — This is a real-time 16-bit readonlyregister that constantly updates to reflect the ORed summaryof the sequence event register set. In general, if bit B1is set, the instrument is in an arm layer. The following SCPIquery command can be used to read the Arm Condition Register::STATus:OPERation:ARM:CONDition?The Arm Condition Register and the Transition Filter areused to set the bits of the Arm Event Register. The TransitionFilter is discussed next.Arm Transition Filter — The transition filter is made up oftwo 16-bit registers that are programmed by the user. It isused to specify which transition (0 to 1, or 1 to 0) of bit B1in the Arm Condition Register will set bit B1 in the ArmEvent Register.The filter can be programmed for positive transitions (PTR),negative transitions (NTR) or both. When an event bit is programmedfor a positive transition, the event bit in the ArmEvent Register will set when the corresponding bit in theArm Condition Register changes from 0 to 1. Conversely,when programmed for a negative transition, the bit in the statusregister will set when the corresponding bit in the conditionregister changes from 1 to 0. The transition filterregisters can be set or cleared by using the following SCPIcommands::STATus:OPERation:ARM:PTR :STATus:OPERation:ARM:NTR The transition filter registers can be read at any time by usingthe following SCPI query commands::STATus:OPERation:ARM:PTR?:STATus:OPERation:ARM:NTR?Reading a transition filter register using the above querycommands does not affect the contents of the register.1. Cycling power.2. Sending the :STATus:PRESet command.3. Sending the :STATus:OPERation:ARM:PTR 65535 and:STATus:OPERation:ARM:NTR 0 commands.Arm Event Register — This is a latched, read-only registerwhose bits are set by the Arm Condition Register and TransitionFilter. Once a bit in this register is set, it will remain set(latched) until the register is cleared by a specific clearingoperation. The bits of this register are logically ANDed withthe bits of the Arm Event Enable Register and applied to anOR gate. The output of the OR gate is the Arm Summary Bitthat is applied to the Operation Condition Register. The followingSCPI query command can be used to read the ArmEvent Register::STATus:OPERation:ARM:EVENt?Reading this register using the above SCPI command clearsthe register. The following list summarizes all operations thatwill clear the Operation Event Register:1. Cycling power.2. Sending the *CLS common command.3. Sending the :STATus:OPERation:ARM? query command.Arm Event Enable Register — This register is programmedby the user and serves as a mask for the Arm Event Register.When masked, a set bit (B1) in the Arm Event Register willnot set the Waiting for Arm bit in the Operation ConditionRegister. Conversely, when unmasked, a set bit (b1) in theArm Event Register will set the Waiting for Arm bit.Bit B1 in the Arm Event Register is masked when the correspondingbit (B1) in the Arm Event Enable Register iscleared (0). When the masked bit of the Arm Event Registersets, it is ANDed with the corresponding cleared bit in theArm Event Enable Register. The logic “0” output of the ANDgate is applied to the input of the OR gate and thus, will notset the Waiting for Arm bit in the Operation Condition Register.The following operations will set (1) all the bits of the PTRregister and reset (0) all the bits of the NTR register:Bit B1 in the Arm Event Register is unmasked when the correspondingbit (B1) in the Arm Event Enable Register is set5-13