UM10211 - Standard ICs

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NXP Semiconductors UM10211 Chapter 10: LPC2300 GPIO Writing to the IOPIN register stores the value in the port output register, bypassing the need to use both the IOSET and IOCLR registers to obtain the entire written value. This feature should be used carefully in an application since it affects the entire port. Legacy registers are the IO0PIN and IO1PIN while the enhanced GPIOs are supported via the FIO0PIN, FIO1PIN, FIO2PIN, FIO3PIN and FIO4PIN registers. Access to a port pin via the FIOPIN register is conditioned by the corresponding bit of the FIOMASK register (see Section 10–4.5 “Fast GPIO port Mask register FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF C0[1/3/5/7/9]0)”). Only pins masked with zeros in the Mask register (see Section 10–4.5 “Fast GPIO port Mask register FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF C0[1/3/5/7/9]0)”) will be correlated to the current content of the Fast GPIO port pin value register. Table 118. GPIO port Pin value register (IO0PIN - address 0xE002 8000 and IO1PIN - address 0xE002 8010) bit description Bit Symbol Value Description Reset value 31:0 P0xVAL or P1xVAL 0 Slow GPIO pin value bits. Bit 0 in IOxPIN corresponds to pin Px.0, bit 31 in IOxPIN corresponds to pin Px.31. Controlled pin output is set to LOW. 1 Controlled pin output is set to HIGH. 0x0 Table 119. Fast GPIO port Pin value register (FIO[0/1/2/3/4]PIN - address 0x3FFF C0[1/3/5/7/9]4) bit description Bit Symbol Value Description Reset value 31:0 FP0xVAL FP1xVAL FP2xVAL FP3xVAL FP4xVAL 0 Fast GPIO output value Set bits. Bit 0 in FIOxCLR corresponds to pin Px.0, bit 31 in FIOxCLR corresponds to pin Px.31. Controlled pin output is set to LOW. 1 Controlled pin output is set to HIGH. Aside from the 32-bit long and word only accessible FIOPIN register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 10–120, too. Next to providing the same functions as the FIOPIN register, these additional registers allow easier and faster access to the physical port pins. 0x0 UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 126 of 613
NXP Semiconductors UM10211 Chapter 10: LPC2300 GPIO Table 120. Fast GPIO port Pin value byte and half-word accessible register description Generic Register name Description Register length (bits) & access Reset value PORTn Register Address & Name FIOxPIN0 FIOxPIN1 FIOxPIN2 FIOxPIN3 FIOxPINL FIOxPINU Fast GPIO Port x Pin value register 0. Bit 0 in FIOxPIN0 register corresponds to pin Px.0 ... bit 7 to pin Px.7. Fast GPIO Port x Pin value register 1. Bit 0 in FIOxPIN1 register corresponds to pin Px.8 ... bit 7 to pin Px.15. Fast GPIO Port x Pin value register 2. Bit 0 in FIOxPIN2 register corresponds to pin Px.16 ... bit 7 to pin Px.23. Fast GPIO Port x Pin value register 3. Bit 0 in FIOxPIN3 register corresponds to pin Px.24 ... bit 7 to pin Px.31. Fast GPIO Port x Pin value Lower half-word register. Bit 0 in FIOxPINL register corresponds to pin Px.0 ... bit 15 to pin Px.15. Fast GPIO Port x Pin value Upper half-word register. Bit 0 in FIOxPINU register corresponds to pin Px.16 ... bit 15 to Px.31. 8 (byte) R/W 8 (byte) R/W 8 (byte) R/W 8 (byte) R/W 16 (half-word) R/W 16 (half-word) R/W 0x00 0x00 0x00 0x00 0x0000 0x0000 FIO0PIN0 - 0x3FFF C014 FIO1PIN0 - 0x3FFF C034 FIO2PIN0 - 0x3FFF C054 FIO3PIN0 - 0x3FFF C074 FIO4PIN0 - 0x3FFF C094 FIO0PIN1 - 0x3FFF C015 FIO1PIN1 - 0x3FFF C035 FIO2PIN1 - 0x3FFF C055 FIO3PIN1 - 0x3FFF C075 FIO4PIN1 - 0x3FFF C095 FIO0PIN2 - 0x3FFF C016 FIO1PIN2 - 0x3FFF C036 FIO2PIN2 - 0x3FFF C056 FIO3PIN2 - 0x3FFF C076 FIO4PIN2 - 0x3FFF C096 FIO0PIN3 - 0x3FFF C017 FIO1PIN3 - 0x3FFF C037 FIO2PIN3 - 0x3FFF C057 FIO3PIN3 - 0x3FFF C077 FIO4PIN3 - 0x3FFF C097 FIO0PINL - 0x3FFF C014 FIO1PINL - 0x3FFF C034 FIO2PINL - 0x3FFF C054 FIO3PINL - 0x3FFF C074 FIO4PINL - 0x3FFF C094 FIO0PINU - 0x3FFF C016 FIO1PINU - 0x3FFF C036 FIO2PINU - 0x3FFF C056 FIO3PINU - 0x3FFF C076 FIO4PINU - 0x3FFF C096 4.5 Fast GPIO port Mask register FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF C0[1/3/5/7/9]0) This register is available in the enhanced group of registers only. It is used to select port pins that will and will not be affected by write accesses to the FIOPIN, FIOSET or FIOCLR register. Mask register also filters out port’s content when the FIOPIN register is read. A zero in this register’s bit enables an access to the corresponding physical pin via a read or write access. If a bit in this register is one, corresponding pin will not be changed with write access and if read, will not be reflected in the updated FIOPIN register. For software examples, see Section 10–5 “GPIO usage notes” on page 131 UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 127 of 613
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UM10211 LPC2364/66/68/78 User manua
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UM10211 - Standard ICs

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