UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 12: LPC2300 CAN1, 2
The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the
CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b)
software clearing SM in the CAN Mode register. A sleeping CAN Controller, that wakes up
in response to bus activity, is not able to receive an initial message, until after it detects
Bus_Free (11 consecutive recessive bits). If an interrupt is pending or the CAN bus is
active when software sets SM, the wake-up is immediate.
7.3 Interrupts
Each CAN Controller produces 3 interrupt requests, Receive, Transmit, and “other status”.
The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers. Each
Receive and Transmit interrupt request from each controller is assigned its own channel in
the Vectored Interrupt Controller (VIC), and can have its own interrupt service routine. The
“other status” interrupts from all of the CAN controllers, and the Acceptance Filter LUTerr
condition, are ORed into one VIC channel.
7.4 Transmit priority
If the TPM bit in the CANxMOD register is 0, multiple enabled Tx Buffers contend for the
right to send their messages based on the value of their CAN Identifier (TID). If TPM is 1,
they contend based on the PRIO fields in bits 7:0 of their CANxTFS registers. In both
cases the smallest binary value has priority. If two (or three) transmit-enabled buffers have
the same smallest value, the lowest-numbered buffer sends first.
The CAN controller selects among multiple enabled Tx Buffers dynamically, just before it
sends each message.
8. Centralized CAN registers
For easy and fast access, all CAN Controller Status bits from each CAN Controller Status
register are bundled together. Each defined byte of the following registers contains one
particular status bit from each of the CAN controllers, in its LS bits.
All Status registers are “read-only” and allow byte, half word and word access.
8.1 Central Transmit Status Register (CANTxSR - 0xE004 0000)
Table 212. Central Transit Status Register (CANTxSR - address 0xE004 0000) bit description
Bit Symbol Description Reset
Value
0 TS1 When 1, the CAN controller 1 is sending a message (same as TS in the 0
CAN1GSR).
1 TS2 When 1, the CAN controller 2 is sending a message (same as TS in the 0
CAN2GSR)
7:2 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
8 TBS1 When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU 1
(same as TBS in CAN1GSR).
9 TBS2 When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU
(same as TBS in CAN2GSR).
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UM10211_1
© NXP B.V. 2007. All rights reserved.
User manual Rev. 01 — 27 March 2007 232 of 613