UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 32: Supplementary information
4. Figures
Fig 1. LPC2364/6/8 block diagram . . . . . . . . . . . . . . . . .8
Fig 2. LPC2378 block diagram . . . . . . . . . . . . . . . . . . . .9
Fig 3. LPC2364/66/68 system memory map . . . . . . . . . 11
Fig 4. LPC2378 system memory map . . . . . . . . . . . . . .12
Fig 5. Peripheral memory map. . . . . . . . . . . . . . . . . . . .13
Fig 6. AHB peripheral map . . . . . . . . . . . . . . . . . . . . . .14
Fig 7. Map of lower memory is showing re-mapped and
re-mappable areas. . . . . . . . . . . . . . . . . . . . . . . .19
Fig 8. Reset block diagram including the wakeup timer.23
Fig 9. Clock generation for the LPC2300. . . . . . . . . . . .33
Fig 10. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . .38
Fig 11. PLL and clock dividers. . . . . . . . . . . . . . . . . . . . .45
Fig 12. EMC block diagram . . . . . . . . . . . . . . . . . . . . . . .57
Fig 13. Simplified block diagram of the Memory Accelerator
Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Fig 14. Block diagram of the Memory Accelerator Module .
75
Fig 15. Block diagram of the Vectored Interrupt Controller .
86
Fig 16. LPC2364/6/8 100 - pin packages. . . . . . . . . . . . .87
Fig 17. LPC2378 144 - pin package . . . . . . . . . . . . . . . .95
Fig 18. Ethernet block diagram . . . . . . . . . . . . . . . . . . .135
Fig 19. Ethernet packet fields . . . . . . . . . . . . . . . . . . . .137
Fig 20. Receive descriptor memory layout. . . . . . . . . . .164
Fig 21. Transmit descriptor memory layout . . . . . . . . . .167
Fig 22. Transmit example memory and registers. . . . . .178
Fig 23. Receive Example Memory and Registers . . . . .184
Fig 24. Transmit Flow Control . . . . . . . . . . . . . . . . . . . .189
Fig 25. Receive filter block diagram. . . . . . . . . . . . . . . .191
Fig 26. Receive Active/Inactive state machine . . . . . . .195
Fig 27. Transmit Active/Inactive state machine . . . . . . .196
Fig 28. CAN controller block diagram . . . . . . . . . . . . . .206
Fig 29. Transmit buffer layout for standard and extended
frame format configurations . . . . . . . . . . . . . . . .207
Fig 30. Receive buffer layout for standard and extended
frame format configurations . . . . . . . . . . . . . . . .208
Fig 31. Global Self-Test (high-speed CAN Bus example) . .
209
Fig 32. Local Self-Test (high-speed CAN Bus example) 209
Fig 33. Entry in FullCAN and individual standard identifier
tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
Fig 34. Entry in standard identifier range table . . . . . . .236
Fig 35. Entry in either extended identifier table . . . . . . .236
Fig 36. ID Look-up table example explaining the search
algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
Fig 37. Semaphore procedure for reading an auto-stored
message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Fig 38. FullCAN section example of the ID look-up table . .
249
Fig 39. FullCAN message object layout . . . . . . . . . . . . 249
Fig 40. Normal case, no messages lost . . . . . . . . . . . . 251
Fig 41. Message lost . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Fig 42. Message gets overwritten . . . . . . . . . . . . . . . . . 252
Fig 43. Message overwritten indicated by semaphore bits
and message lost . . . . . . . . . . . . . . . . . . . . . . . 253
Fig 44. Message overwritten indicated by message lost254
Fig 45. Clearing message lost. . . . . . . . . . . . . . . . . . . . 255
Fig 46. Detailed example of acceptance filter tables and ID
index values . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Fig 47. ID Look-up table configuration example (no
FullCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Fig 48. ID Look-up table configuration example (FullCAN
activated and enabled) . . . . . . . . . . . . . . . . . . . 261
Fig 49. USB device controller block diagram . . . . . . . . 265
Fig 50. USB MaxPacketSize register array indexing . . 283
Fig 51. Interrupt event handling . . . . . . . . . . . . . . . . . . 295
Fig 52. UDCA Head register and DMA Descriptors . . . 308
Fig 53. Isochronous OUT endpoint operation example. 316
Fig 54. Data transfer in ATLE mode . . . . . . . . . . . . . . . 317
Fig 55. Autobaud a) mode 0 and b) mode 1 waveform 335
Fig 56. LPC2300 UART0, 2 and 3 block diagram . . . . . 340
Fig 57. Auto-RTS Functional Timing . . . . . . . . . . . . . . . 352
Fig 58. Auto-CTS Functional Timing . . . . . . . . . . . . . . . 353
Fig 59. Auto-baud a) mode 0 and b) mode 1 waveform 359
Fig 60. LPC2300 UART1 block diagram . . . . . . . . . . . . 364
Fig 61. SPI data transfer format (CPHA = 0 and CPHA = 1)
366
Fig 62. SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . 375
Fig 63. Texas Instruments Synchronous Serial Frame
Format: a) Single and b) Continuous/back-to-back
Two Frames Transfer . . . . . . . . . . . . . . . . . . . . 378
Fig 64. SPI Frame Format with CPOL=0 and CPHA=0 (a)
Single and b) Continuous Transfer) . . . . . . . . . 379
Fig 65. SPI Frame Format with CPOL=0 and CPHA=1 380
Fig 66. SPI Frame Format with CPOL = 1 and CPHA = 0 (a)
Single and b) Continuous Transfer) . . . . . . . . . 381
Fig 67. SPI Frame Format with CPOL = 1 and CPHA = 1 .
382
Fig 68. Microwire Frame Format (Single Transfer) . . . . 383
Fig 69. Microwire Frame Format (Continuos Transfers) 384
Fig 70. Microwire frame format setup and hold details . 384
Fig 71. Multimedia card system . . . . . . . . . . . . . . . . . . 392
Fig 72. Secure digital memory card connection . . . . . . 392
Fig 73. MCI adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Fig 74. Command path state machine . . . . . . . . . . . . . 394
Fig 75. MCI command transfer . . . . . . . . . . . . . . . . . . . 395
continued >>
UM10211_1
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User manual Rev. 01 — 27 March 2007 595 of 613