UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 11: LPC2300 Ethernet
16. Interrupts
The hardware will receive packets from the PHY and apply filtering as configured by the
software driver. While receiving a packet the hardware will read a descriptor from memory
to find the location of the associated receiver data buffer. Receive data is written in the
data buffer and receive status is returned in the receive descriptor status word. Optionally
an interrupt can be generated to notify software that a packet has been received. Note
that the DMA manager will prefetch and buffer up to three descriptors.
15.2 AHB interface
The registers of the Ethernet block connect to an AHB slave interface to allow access to
the registers from the CPU.
The AHB interface has a 32 bit data path, which supports only word accesses and has an
address aperture of 4 kB. Table 11–133 lists the registers of the Ethernet block.
All AHB write accesses to registers are posted except for accesses to the IntSet, IntClear
and IntEnable registers. AHB write operations are executed in order.
If the PowerDown bit of the PowerDown register is set, all AHB read and write accesses
will return a read or write error except for accesses to the PowerDown register.
Bus Errors
The Ethernet block generates errors for several conditions:
• The AHB interface will return a read error when there is an AHB read access to a
write-only register; likewise a write error is returned when there is an AHB write
access to the read-only register. An AHB read or write error will be returned on AHB
read or write accesses to reserved registers. These errors are propagated back to the
CPU. Registers defined as read-only and write-only are identified in Table 11–133.
• If the PowerDown bit is set all accesses to AHB registers will result in an error
response except for accesses to the PowerDown register.
The Ethernet block has a single interrupt request output to the CPU (via the Vectored
Interrupt Controller).
The interrupt service routine must read the IntStatus register to determine the origin of the
interrupt. All interrupt statuses can be set by software writing to the IntSet register;
statuses can be cleared by software writing to the IntClear register.
The transmit and receive datapaths can only set interrupt statuses, they cannot clear
statuses. The SoftInt interrupt cannot be set by hardware and can be used by software for
test purposes.
16.1 Direct Memory Access (DMA)
Descriptor arrays
The Ethernet block includes two DMA managers. The DMA managers make it possible to
transfer frames directly to and from memory with little support from the processor and
without the need to trigger an interrupt for each frame.
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User manual Rev. 01 — 27 March 2007 170 of 613