UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 12: LPC2300 CAN1, 2
Table 217. Acceptance Filter Mode Register (AFMR - address 0xE003 C000) bit description
Bit Symbol Value Description Reset
Value
0 AccOff [2] 1 if AccBP is 0, the Acceptance Filter is not operational. All Rx 1
messages on all CAN buses are ignored.
1 AccBP [1] 1 All Rx messages are accepted on enabled CAN controllers.
Software must set this bit before modifying the contents of any of
the registers described below, and before modifying the contents
of Lookup Table RAM in any way other than setting or clearing
Disable bits in Standard Identifier entries. When both this bit and
AccOff are 0, the Acceptance filter operates to screen received
CAN Identifiers.
0
2 eFCAN [3] 0 Software must read all messages for all enabled IDs on all
enabled CAN buses, from the receiving CAN controllers.
1 The Acceptance Filter itself will take care of receiving and storing
messages for selected Standard ID values on selected CAN
buses. See Section 12–15 “FullCAN mode” on page 244.
31:3 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
[1] Acceptance Filter Bypass Mode (AccBP): By setting the AccBP bit in the Acceptance Filter Mode Register,
the Acceptance filter is put into the Acceptance Filter Bypass mode. During bypass mode, the internal state
machine of the Acceptance Filter is reset and halted. All received CAN messages are accepted, and
acceptance filtering can be done by software.
[2] Acceptance Filter Off mode (AccOff): After power-upon hardware reset, the Acceptance filter will be in Off
mode, the AccOff bit in the Acceptance filter Mode register 0 will be set to 1. The internal state machine of
the acceptance filter is reset and halted. If not in Off mode, setting the AccOff bit, either by hardware or by
software, will force the acceptance filter into Off mode.
[3] FullCan Mode Enhancements: A FullCan mode for received CAN messages can be enabled by setting the
eFCAN bit in the acceptance filter mode register.
13.2 Section configuration registers
The 10 bit section configuration registers are used for the ID look-up table RAM to indicate
the boundaries of the different sections for explicit and group of CAN identifiers for 11 bit
CAN and 29 bit CAN identifiers, respectively. The 10 bit wide section configuration
registers allow the use of a 512x32 (2 kB) look-up table RAM. The whole ID Look-up Table
RAM is only word accessible. All five section configuration registers contain APB
addresses for the acceptance filter RAM and do not include the APB base address. A
write access to all section configuration registers is only possible during the Acceptance
filter off and Bypass modes. Read access is allowed in all acceptance filter modes.
0
NA
UM10211_1
© NXP B.V. 2007. All rights reserved.
User manual Rev. 01 — 27 March 2007 238 of 613