UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 28: LPC2300 GPDMA
9. Channel registers
Table 528. Synchronization register (DMACSync - address 0xFFE0 4034) bit description
Bit Symbol Description Reset
Value
15:0 DMACSync DMA synchronization logic for DMA request signals enabled or
disabled. A LOW bit indicates that the synchronization logic for
the DMACBREQ[15:0], DMACSREQ[15:0],
DMACLBREQ[15:0], and DMACLSREQ[15:0] request signals
is enabled. A HIGH bit indicates that the synchronization logic
is disabled.
0x0000
31:16 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The channel registers are used to program the two DMA channels. These registers
consist of:
• Two DMACCxSrcAddr Registers
• Two DMACCxDestAddr Registers
• Two DMACCxLLI Registers
• Two DMACCxControl Registers
• Two DMACCxConfiguration Registers
When performing scatter/gather DMA the first four registers are automatically updated.
9.1 Channel Source Address Registers (DMACC0SrcAddr - 0xFFE0 4100
and DMACC1SrcAddr - 0xFFE0 4120)
The two read/write DMACCxSrcAddr Registers contain the current source address
(byte-aligned) of the data to be transferred. Each register is programmed directly by
software before the appropriate channel is enabled. When the DMA channel is enabled
this register is updated:
• As the source address is incremented.
• By following the linked list when a complete packet of data has been transferred.
Reading the register when the channel is active does not provide useful information. This
is because by the time software has processed the value read, the channel might have
progressed. It is intended to be read only when the channel has stopped, in which case it
shows the source address of the last item read.
Note: The source and destination addresses must be aligned to the source and
destination widths.
Table 28–529 shows the bit assignments of the DMACCxSrcAddr Registers.
Table 529. Channel Source Address registers (DMACC0SrcAddr - address 0xFFE0 4100 and
DMACC1SrcAddr - address 0xFFE0 4120) bit description
Bit Symbol Description Reset Value
31:0 SrcAddr DMA source address. 0x0000 0000
NA
UM10211_1
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User manual Rev. 01 — 27 March 2007 550 of 613